PIC17C756-33I/L Microchip Technology, PIC17C756-33I/L Datasheet - Page 60

• Manufacturer Part Number: PIC17C756-33I/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

8.3
The table read allows the program memory to be read.
This allows constants to be stored in the program
memory space, and retrieved into data memory when
needed. Example 8-2 reads the 16-bit value at pro-
gram memory address TBLPTR. After the dummy byte
has been read from the TABLATH, the TABLATH is
loaded with the 16-bit data from program memory
address TBLPTR + 1. The first read loads the data into
the latch, and can be considered a dummy read
(unknown data loaded into 'f'). INDF0 should be con-
figured for either auto-increment or auto-decrement.
FIGURE 8-7:
FIGURE 8-8:
DS30264A-page 60
Instruction
fetched
AD15:AD0
Instruction
executed
Table Reads
WR
ALE
OE
AD15:AD0
Instruction
fetched
Instruction
executed
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'1'
TABLRD TIMING
TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
INST (PC-1)
TABLRD1
ALE
PC
WR
OE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'1'
TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cycle2
INST (PC-1)
TABLRD
TABLRD2
PC
PC+1
TABLRD cycle1
Data read cycle
Preliminary
INST (PC+1)
PC+1
TBL1 Data in 1
EXAMPLE 8-2:
MOVLW
MOVWF
MOVLW
MOVWF
TABLRD
TLRD
TABLRD
INST (PC+2)
Data read cycle
TABLRD cycle2
PC+2
TBL
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
0,0,DUMMY
1, INDF0
0,1,INDF0
Data in
Data read cycle
TABLE READ
TBL2 Data in 2
INST (PC+2)
INST (PC+1)
1997 Microchip Technology Inc.
PC+2
; Dummy read,
;
; Read HI byte
;
; Read LO byte
;
;
;
;
;
Updates TABLATH
of TABLATH
of TABLATH and
Update TABLATH
INST (PC+3)
INST (PC+2)
address
PC+3