PIC17C756-33I/L Microchip Technology, PIC17C756-33I/L Datasheet - Page 93

• Manufacturer Part Number: PIC17C756-33I/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

FIGURE 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7)
1997 Microchip Technology Inc.
bit7
bit 7:
bit 6:
bit 5:
bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits
bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits
bit 0:
U-0
-
Unimplemented: Read as ‘0’
CA4OVF: Capture4 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture4 registers
0 = No overflow occurred on Capture4 registers
CA3OVF: Capture3 Overflow Status bit
This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L)
before the next capture event occurred. The capture register retains the oldest unread capture value (last
capture before overflow). Subsequent capture events will not update the capture register with the TMR3
value until the capture register has been read (both bytes).
1 = Overflow occurred on Capture3 registers
0 = No overflow occurred on Capture3 registers
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
00 = Capture on every falling edge
01 = Capture on every rising edge
10 = Capture on every 4th rising edge
11 = Capture on every 16th rising edge
PWM3ON: PWM3 On bit
1 = PWM3 is enabled (The RG5/PWM3 pin ignores the state of the DDRG<5> bit)
0 = PWM3 is disabled (The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)
CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
R - 0
R - 0
R/W - 0
R/W - 0
Preliminary
R/W - 0
R/W - 0
R/W - 0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
Reads as ‘0’
-n = Value at POR reset
DS30264A-page 93