AT90S8535-8AI Atmel, AT90S8535-8AI Datasheet - Page 20

• Manufacturer Part Number: AT90S8535-8AI
• Description: IC MCU 8K 8MHZ A/D IT 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8535-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Stack Pointer – SP
Reset and Interrupt
Handling
20
AT90S/LS8535
The AT90S8535 Stack Pointer is implemented as two 8-bit registers in the I/O space
locations $3E ($5E) and $3D ($5D). As the AT90S8535 data memory has $25F loca-
tions, 10 bits are used.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Inter-
rupt stacks are located. This stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when
data is pushed onto the stack with the PUSH instruction and it is decremented by 2
when an address is pushed onto the stack with subroutine calls and interrupts. The
Stack Pointer is incremented by 1 when data is popped from the stack with the POP
instruction and it is incremented by 2 when an address is popped from the stack with
return from subroutine RET or return from interrupt RETI.
The AT90S8535 provides 16 different interrupt sources. These interrupts and the sepa-
rate reset vector each have a separate program vector in the program memory space.
All interrupts are assigned individual enable bits that must be set (one) together with the
I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 (the External
Interrupt Request 0), etc.
Table 2. Reset and Interrupt Vectors
Bit
$3E ($5E)
$3D ($5D)
Read/Write
Initial Value
Vector No.
10
11
12
1
2
3
4
5
6
7
8
9
Program Address
SP7
R/W
15
R
–
7
0
0
$00A
$00B
$000
$001
$002
$003
$004
$005
$006
$007
$008
$009
SP6
R/W
14
R
–
6
0
0
SP5
R/W
13
R
–
5
0
0
Source
RESET
INT0
INT1
TIMER2 COMP
TIMER2 OVF
TIMER1 CAPT
TIMER1 COMPA
TIMER1 COMPB
TIMER1 OVF
TIMER0 OVF
SPI, STC
UART, RX
SP4
R/W
12
R
–
4
0
0
SP3
R/W
11
R
–
3
0
0
Interrupt Definition
Hardware Pin, Power-on Reset and
Watchdog Reset
External Interrupt Request 0
External Interrupt Request 1
Timer/Counter2 Compare Match
Timer/Counter2 Overflow
Timer/Counter1 Capture Event
Timer/Counter1 Compare Match A
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter0 Overflow
SPI Serial Transfer Complete
UART, Rx Complete
SP2
R/W
10
R
–
2
0
0
R/W
R/W
SP9
SP1
9
1
0
0
R/W
R/W
SP8
SP0
8
0
0
0
1041H–11/01
SPH
SPL