AT90S8535-8AI Atmel, AT90S8535-8AI Datasheet - Page 59

• Manufacturer Part Number: AT90S8535-8AI
• Description: IC MCU 8K 8MHZ A/D IT 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8535-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART
Data Transmission
1041H–11/01
The AT90S8535 features a full duplex (separate receive and transmit registers) Univer-
sal Asynchronous Receiver and Transmitter (UART). The main features are:
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A block schematic of the UART transmitter is shown in Figure 41.
Figure 41. UART Transmitter
Data transmission is initiated by writing the data to be transmitted to the UART I/O Data
Register, UDR. Data is transferred from UDR to the Transmit shift register when:
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If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the
shift register. The UDRE (UART Data Register Empty) bit in the UART Status Register,
USR, is set. When this bit is set (one), the UART is ready to receive the next character.
At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0
of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word
Baud Rate Generator that can Generate a Large Number of Baud Rates (bps)
High Baud Rates at Low XTAL Frequencies
8 or 9 Bits Data
Noise Filtering
Overrun Detection
Framing Error Detection
False Start Bit Detection
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Buffered Transmit and Receive
A new character is written to UDR after the stop bit from the previous character has
been shifted out. The shift register is loaded immediately.
A new character is written to UDR before the stop bit from the previous character
has been shifted out. The shift register is loaded when the stop bit of the character
currently being transmitted is shifted out.
AT90S/LS8535
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