AT90S8535-8AI Atmel, AT90S8535-8AI Datasheet - Page 51

• Manufacturer Part Number: AT90S8535-8AI
• Description: IC MCU 8K 8MHZ A/D IT 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8535-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EEPROM Read/Write
Access
EEPROM Address Register –
EEARH and EEARL
EEPROM Data Register –
EEDR
EEPROM Control Register –
EECR
1041H–11/01
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 2.5 - 4 ms, depending on the V
self-timing function lets the user software detect when the next byte can be written. A
special EEPROM Ready interrupt can be set to trigger when the EEPROM is ready to
accept new data.
In order to prevent unintentional EEPROM writes, a specific write procedure must be fol-
lowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed. When the EEPROM is written, the CPU is halted for two clock
cycles before the next instruction is executed.
The EEPROM address registers (EEARH and EEARL) specify the EEPROM address in
the 512-byte EEPROM space. The EEPROM data bytes are addressed linearly
between 0 and 511.
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to
the EEPROM in the address given by the EEAR register. For the EEPROM read opera-
tion, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
• Bit 7..4 – Res: Reserved Bits
These bits are reserved bits in the AT90S8535 and will always read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
When the I-bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is
enabled. When cleared (zero), the interrupt is disabled. The EEPROM Ready Interrupt
generates a constant interrupt when EEWE is cleared (zero).
Bit
$1F ($3F)
$1E ($3E)
Read/Write
Initial Value
Bit
$1D ($3D)
Read/Write
Initial Value
Bit
$1C ($3C)
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
15
R
X
R
–
7
0
7
0
7
–
0
EEAR6
R/W
R/W
14
R
X
R
–
6
0
6
0
6
–
0
EEAR5
R/W
R/W
13
R
X
R
–
5
0
5
0
5
–
0
EEAR4
R/W
R/W
12
R
R
–
4
0
X
4
0
4
–
0
EEAR3
EERIE
R/W
R/W
R/W
11
R
X
–
3
0
3
0
3
0
EEMWE
EEAR2
R/W
R/W
R/W
10
R
X
–
2
0
2
0
2
0
AT90S/LS8535
EEAR1
EEWE
R/W
R/W
R/W
R
X
9
–
1
0
1
0
1
0
EEAR8
EEAR0
EERE
R/W
R/W
LSB
R/W
R/W
CC
8
0
X
X
0
0
0
0
voltages. A
EECR
EEARH
EEARL
EEDR
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