AT90S8535-8AI Atmel, AT90S8535-8AI Datasheet - Page 44

• Manufacturer Part Number: AT90S8535-8AI
• Description: IC MCU 8K 8MHZ A/D IT 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8535-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Timer/Counter2 – TCNT2
Timer/Counter2 Output
Compare Register – OCR2
44
AT90S/LS8535
When the prescaler is set to divide by 8, the timer will count like this:
... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0,
0, 0, 0, 0, 0, 0 | 1, 1, 1,...
In PWM mode, this bit has no effect.
• Bits 2, 1, 0 – CS22, CS21, CS20: Clock Select Bits 2, 1 and 0
The Clock Select bits 2,1 and 0 define the prescaling source of Timer/Counter2.
Table 18. Timer/Counter2 Prescale Select
The Stop condition provides a Timer Enable/Disable function. The prescaled CK modes
are scaled directly from the CK oscillator clock.
This 8-bit register contains the value of Timer/Counter2.
Timer/Counter2 is realized as an up or up/down (in PWM mode) counter with read and
write access. If the Timer/Counter2 is written to and a clock source is selected, it contin-
ues counting in the timer clock cycle following the write operation.
The Output Compare Register is an 8-bit read/write register.
The Timer/Counter Output Compare Register contains the data to be continuously com-
pared with Timer/Counter2. Actions on compare matches are specified in TCCR2. A
compare match only occurs if Timer/Counter2 counts to the OCR2 value. A software
write that sets TCNT2 and OCR2 to the same value does not generate a compare
match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the
compare event.
Bit
$24 ($44)
Read/Write
Initial Value
Bit
$23 ($43)
Read/Write
Initial Value
CS22
0
0
0
0
1
1
1
1
MSB
MSB
R/W
R/W
7
0
7
0
CS21
0
0
1
1
0
0
1
1
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
CS20
0
1
0
1
0
1
0
1
R/W
R/W
4
0
4
0
Description
Timer/Counter2 is stopped.
PCK2
PCK2/ 8
PCK2/ 32
PCK2/ 64
PCK2/128
PCK2/256
PCK2/1024
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
LSB
R/W
LSB
R/W
0
0
0
0
1041H–11/01
TCNT2
OCR2