AT90S8535-8AI Atmel, AT90S8535-8AI Datasheet - Page 69

• Manufacturer Part Number: AT90S8535-8AI
• Description: IC MCU 8K 8MHZ A/D IT 44TQFP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S8535-8AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Operation
Prescaling
1041H–11/01
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents AGND and the maximum value repre-
sents the voltage on the AREF pin minus one LSB. The analog input channel is selected
by writing to the MUX bits in ADMUX. Any of the eight ADC input pins ADC7..0 can be
selected as single-ended inputs to the ADC.
The ADC can operate in two modes – Single Conversion and Free Running. In Single
Conversion Mode, each conversion will have to be initiated by the user. In Free Running
Mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR
bit in ADCSR selects between the two available modes.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSR. Input channel
selections will not go into effect until ADEN is set. The ADC does not consume power
when ADEN is cleared, so it is recommended to switch off the ADC before entering
power-saving sleep modes.
A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be set to zero by
hardware when the conversion is completed. If a different data channel is selected while
a conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
The ADC generates a 10-bit result, which is presented in the ADC data register, ADCH
and ADCL. When reading data, ADCL must be read first, then ADCH, to ensure that the
content of the data register belongs to the same conversion. Once ADCL is read, ADC
access to data register is blocked. This means that if ADCL has been read and a con-
version completes before ADCH is read, neither register is updated and the result from
the conversion is lost. Then ADCH is read, ADC access to the ADCH and ADCL register
is re-enabled.
The ADC has its own interrupt that can be triggered when a conversion completes.
When ADC access to the data registers is prohibited between reading of ADCH and
ADCL, the interrupt will trigger even if the result is lost.
Figure 46. ADC Prescaler
The successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to achieve maximum resolution. If a resolution of lower than 10 bits is
required, the input clock frequency to the ADC can be higher than 200 kHz to achieve a
ADEN
ADPS0
ADPS1
ADPS2
CK
Reset
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
AT90S/LS8535
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