HSP50415EVAL1 Intersil, HSP50415EVAL1 Datasheet
HSP50415EVAL1
Specifications of HSP50415EVAL1
Related parts for HSP50415EVAL1
HSP50415EVAL1 Summary of contents
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... Digital Signal Processing Capable of >70dB SFDR • Dual 12-bit D/A Processing Capable of >50dB SFDR • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • Wide-Band Digital Modulation • Base Station Modulators • HSP50415EVAL1 Evaluation Board Available TEMP RANGE (°C) PACKAGE -40 to +85 100 Ld MQFP -40 to +85 100 Ld MQFP (Pb-free) CAUTION: These devices are sensitive to electrostatic discharge ...
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Pinout CDATA0 CDATA1 CDATA2 VDD CDATA3 CDATA4 GND CDATA5 CDATA6 CDATA7 RD WR GND CE ADDR0 ADDR1 ADDR2 REFCLK 2XSYMCLK INTREQ NC VDD RESET CLK GND DVDD DGND PLLRC PGND PVDD Block Diagram W/R μP INTERFACE CONTROL DATA DATA INTERFACE/ ...
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Functional Block Diagram μP RESET INTERFACE ADDR<2:0> CDATA<7:0> INTREQ x2 INTERPOLATION DIN<15:0> CONST. I MAP ISTRB FIR DATACLK BYPASS DATA TXEN INTERFACE/ FEMPT FIFO FOVRFL FFULL Q FIR BYPASS BYPASS 2XSYMCLK X 2 PHASE ...
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Pin Descriptions NAME TYPE VDD - Digital power. GND - Digital ground. DVDD - DAC digital power. DGND - DAC digital ground. AVDD - DAC analog power. AGND - DAC analog ground. PVDD - PLL analog power. PGND - PLL ...
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Pin Descriptions (Continued) NAME TYPE ICOMP1, I Compensation Pin for use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to AVDD with QCOMP1 a 0.1μF capacitor. To minimize crosstalk, the part was designed so that these pins must be ...
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A MATLAB or Excel program for calculating the component values is available. For improved APLL performance, utilization of specific calculated values is recommended over the general purpose ones shown in Figure 1. Symbol NCO As the data flows through the ...
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The SYMBOL NCO 32-bit Phinc value is adjusted automatically such that the SYMBOL NCO runs at the input rate of the interpolating filter, since this is the fastest rate prior to the FSout rate. Table 1 lists possible filter configurations ...
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NCO divider<13:0> REFCLK divider<7:0> 8-BIT COUNTER REFCLK TC 14-bit countValue enable SYNC CLK frequencyGain freqError<15:0> lagGain phaseError<21:0> leadGain positive lockedValue negative notLockedValue threshold<20:0> phaseErrorMag<20:0> analogPLLlockStatus useAPLLlockStatus The Lock Detector compares the magnitude of the phaseError to a programmable 21-bit threshold ...
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Front-End Data Input Block The HSP50415 accepts input data in a parallel bit fashion with I and Q samples input serially as shown in Figure 5. The signal pins on the device that input data to the front-end are the ...
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Iout<3:0>:Qout<3:0>. See Figure 7 for a constellation mapping example. For bit widths less than 4-bits the data in the RAM may simply be zero’s for the unused bit positions and the unused addresses since the HSP50415 will discard the unused ...
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The extra bit is carried to check for overflow at the output of the shifter. The output of the multiplier (multOut<22:6>) is then shifted to the appropriate position per ...
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Typical Performance Curves 0 -10 INTERPOLATION FILTER RESPONSE -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 512 1024 1536 2048 2560 SAMPLE TIMES FIGURE 9. RESPONSE FOR L = 16; FOUT = 4096 0.1 0 -0.1 ...
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Typical Performance Curves 0 INTERPOLATION FILTER RESPONSE -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 512 1024 SAMPLE TIMES FIGURE 15. RESPONSE FOR FOUT = 4096 -100 -110 -120 Carrier NCO and ...
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NORMALIZED FREQUENCY FIGURE 18. X/SIN(X) FILTER RESPONSE I/Q Gain Imbalance Correction Stage Following the X/SIN(X) filter pair is a gain stage where I and ...
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These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 19). With the center tap ...
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WR ADDR<2:0> CDATA<7:0> FIGURE 20. CONTROL REGISTER LOADING SEQUENCE There should be at least 4 digital core clock cycles between writing to address 4 and reloading the MasterReg as the data from ...
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Table 9 demonstrates the sequence of writes necessary to load memory location 0 of the I and Q channel coefficient RAMs simultaneously. If auto-increment address mode had been enabled, then the ...
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When writing to the constellation map RAM, when the word select counter is equal to 0 and a memUpdate strobe occurs, memBuf<71:64> data is written to memAddr<7:0> of the constellation map RAM. When reading back the memories, The sequence is ...
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ADDRESS BIT WIDTH 00 8 Memory Write/Read Controls Device Configuration Controls FIFO And I/O Control FIFO Upper Threshold and I Channel Gain FIFO Lower Threshold and Q Channel ...
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TABLE 15. DEVICE CONFIGURATION CONTROL (Continued) BIT NO. 12 2-bit Filter Mode. Input data at 2x rate with ½ # taps used. 11:10 Shaping Filter Interpolation 16x ...
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BIT NO. 17 FIFO TXEN Gated Read 0 = FIFO reads not gated by TXEN (reads begin after 2 FIFO locations written TXEN Pin gates read from FIFO 16 FIFO Underflow/Empty Pin Function 0 = Output FIFO underflow ...
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BIT NO. 31:24 FIFO Threshold Lower Limit<7:0> 23:14 Q Scale Factor<9:0> 13 Offset <9:0> Negate Scale Factor 2 Q Subtract DC Offset 1:0 Q Programmable Round Rounding Round to 14-bits ...
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BIT NO. 31 Use Analog PLL lock status bit for Lock Detection 30:28 Analog PLL VCO divider 000 = 1x B 001 = 2x B 010 = 4x B 011 = 8x B 100 = 16x B 101 = 32x ...
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BIT NO. 7 Not Used 6 FIFO Full 5 FIFO Empty 4 FIFO Overflow 3 FIFO Underflow 2 Digital PLL Lock Detect 1 Analog PLL Lock Detect 0 Reset Done BIT NO. 31:0 Carrier NCO Frequency Step BIT NO. 31:0 ...
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... ADDRESS = 12 H DESCRIPTION Evaluation Kit The HSP50415EVAL1 is an evaluation kit for the HSP50415 wideband programmable modulator. The kit consists of an evaluation Circuit Card Assembly complete with the HSP50415 device and additional circuitry to provide for control via a computer parallel port. Windows based ...
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Absolute Maximum Ratings Supply Voltage (VDD to GND .6V All Signal Pins . ...
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VDD = +3.3V ±5%, T Electrical Specifications PARAMETER DATACLK Low, t DCL Setup Time Hold Time CHARACTERISTICS: DIGITAL STATUS / DATA REFCLK Frequency, f RCK REFCLK High, t RCH REFCLK Low, t RCL Digital Status ...
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Waveforms CLK t t CLK RTS t RESET FIGURE 22. CLK AND RELATIVE RESET TIMING WR CDATA<7:0>, ADDR<2:0>, AND FIGURE 24. TIMING RELATIVE TO WR, LOADING SEQUENCE AND ADDR. ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...