HSP50415EVAL1 Intersil, HSP50415EVAL1 Datasheet - Page 9

• Manufacturer Part Number: HSP50415EVAL1
• Description: EVALUATION BOARD HSP50415VI
• Manufacturer: Intersil
• Type: Modulator, Demodulatorr

Specifications of HSP50415EVAL1

• For Use With/related Products: HSP50415
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Front-End Data Input Block
The HSP50415 accepts input data in a parallel bit fashion
with I and Q samples input serially as shown in Figure 5. The
signal pins on the device that input data to the front-end are
the DIN<15:0> bus, the ISTRB and TXEN control pins and
the DATACLK pin.
All data is synchronous to the DATACLK. Further references
to bit-widths will be with respect to a single channel (I and Q
channels are identical). The input data may be from 1-bit up
to 16-bits wide with bits positioned on the LSB’s of the bus.
The data samples are input as I then Q serially with the
ISTRB pin active with the I sample. The maximum data rate
is 50MHz at FSout of 100MHz or twice the maximum symbol
rate. The data written into the chip may be gated with the
TXEN pin (burst Mode) or input free-running. The ISTRB
and TXEN pins have user-programmable active states thus
allowing spectral inversion to be implemented by simply
changing the ISTRB polarity. Figure 6 shows the input data
timing (assuming the ISTRB pin is an active high).
Once a valid pair of I and Q samples has been received, the
data pair is written into the 256x32-bit FIFO. The data is read
out of the FIFO at the symbol rate using the internally
generated symbol clock which is synchronous to the clock
pin. This internally generated symbol clock is available on
the 2XSYMCLK pin of the chip. It has been multiplied up to
twice the symbol rate to facilitate tying it to the DATACLK pin
in symbol rate synchronous modes. The data is always input
to the chip at twice the rate at which it is written to the FIFO
since I and Q are input serially. In a symbol rate synchronous
mode, the data is input to the front-end at twice the symbol
rate, written to the FIFO at the symbol rate and read from the
FIFO also at the symbol rate. This mode ensures that no
FIFO overflow or underflow conditions will occur. Optionally,
in a totally synchronous mode, the FIFO may be bypassed
altogether if power conservation is critical.
Reading data out of the FIFO for transmission may be
optionally gated by the TXEN pin if the user wishes to burst
the data into the chip and delay transmission of the data. If
Iin<15:0>, Qin<15:0>
FIGURE 5. SERIAL TO PARALLEL DATA CONVERSION
serial Data Stream
at symbol Rate x2
DATACLK
DIN<15:0>
ISTRB
FIGURE 6. I/Q INPUT DATA TIMING
I
DATA INPUT
FRONT END
BLOCK
9
Q
I
Iout<15:0>
Qout<15:0>
at symbol rate
Q
HSP50415
the data reads are not gated, then after 2 FIFO locations
have been written, data reads are initiated. Via user-
programmable bits, the data may be zeroed leaving the
front-end if the FIFO runs out of data or in gated-read mode,
if the TXEN pin is inactive. Conversely, writing data into the
FIFO may be optionally disabled upon a FIFO full condition.
Control of the starting address for the gated reads is user-
programmable where the address may be zeroed upon start
of transmission or simply incremented from where it left off
on the last transmission.
The FIFO logic contains user programmable threshold
detection (high and low thresholds) as well as full/empty
detection. There are 4 status flags available to the user for
FIFO level monitoring: FIFOOverFlow (FOVRFL), FIFOFull
(FFULL), FIFOUnderFlow, and FIFO empty (FEMPT). These
status flags may be monitored via 3 output pins: the
underflow and empty share one pin with a user selectable
function. Any one of these flags may be used to trigger an
interrupt on the INTREQ pin if the mask register for that
status bit is set. A rising edge of the status signal will set the
interrupt status register bit and cause an external interrupt if
enabled. The only way to clear the status bit and INTREQ
pin is to write a “1” to the corresponding status register bit.
Another feature of the FIFO is the adaptive symbol rate
control logic. The internal symbol rate of the device is
controlled by the digital PLL if enabled. Since the data is
read out of the FIFO at the internal symbol rate, there may
arise a need for the FIFO to adjust the symbol rate if the data
is not being written in and read out at the same rate. This is
achieved by either adding or subtracting a frequency error
term to the digital PLL’s loop filter frequency term or by
forcing the loop filter lag term to its programmed limit. If a
FIFO overflow occurs, then the data is being written into the
FIFO faster than it is being read out, which indicates the
symbol rate needs to be increased thus speeding up the
reads. This scenario would cause the FIFO to try to increase
the final symbol rate error term by either adding the FIFO
frequency error term (user programmable) to the loop filter’s
frequency error term or force the loop filter lag accumulator
to its programmed upper limit. If a FIFO underflow occurs,
then the data is being read out of the FIFO faster than it is
being written in and the FIFO would attempt to slow down
the symbol rate by subtracting the frequency error term or by
forcing the lag accumulator to its lower limit. This adaptive
rate control is user programmable via Register 2 bits 21:20.
Constellation Mapper
The I/Q data pair from the Front End Input Block enters the
constellation mapper at the internal symbol rate and is
mapped via a user programmable look up table to new
symbol data. The symbol mapping is only supported for I/Q
bit widths of 4-bits (256-QAM) or less. The I data is
concatenated with the Q data to form the 8-bit address
(Iin<3:0>:Qin<3:0>) to the 256x8-bit RAM. The 8-bit data
output from the RAM is the new symbol data in the form
April 23, 2007
FN4559.6