HSP50415EVAL1 Intersil, HSP50415EVAL1 Datasheet - Page 15

• Manufacturer Part Number: HSP50415EVAL1
• Description: EVALUATION BOARD HSP50415VI
• Manufacturer: Intersil
• Type: Modulator, Demodulatorr

Specifications of HSP50415EVAL1

• For Use With/related Products: HSP50415
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 19).
With the center tap grounded, the output swing of I/QOUTA
and I/QOUTB will be biased at zero volts. The loading as
shown in Figure 19 will result in a 500mV signal at the output
of the transformer if the full scale output current of the DAC
is set to 20mA. V
~12.5Ω.
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. Since the DACs output voltage
compliance range is -0.3V to +1.25V, the center tap may
need to be left floating or DC offset in order to increase the
amount of signal swing available. The 50Ω load on the
output of the transformer represents the spectrum analyzer’s
input impedance.
Definition of DAC Specifications
Differential Linearity Error, DNL, is the measure of the
step size output deviation from code to code. Ideally the step
size should be 1 LSB. A DNL specification of 1 LSB or less
guarantees monotonicity.
Full Scale Gain Drift, is measured by setting the data inputs
to be all logic high (all 1s) and measuring the output voltage
through a known resistance as the temperature is varied
from T
from the value measured at room temperature to the value
measured at either T
(full scale range) per
Full Scale Gain Error , is the error from an ideal ratio of 32
between the output current and the full scale adjust current
(through R
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Internal Reference Voltage Drift, is defined as the
maximum deviation from the value measured at room
temperature to the value measured at either T
The units are ppm per
LOADING EACH OUTPUT
R
HSP50415
EQ
IS THE IMPEDANCE
MIN
SET
to T
I/QOUTB
I/QOUTA
).
MAX
FIGURE 19. DAC OUTPUTS
OUT
. It is defined as the maximum deviation
MIN
o
= 2 x I
C.
o
C.
or T
100Ω
50Ω
50Ω
OUT
MAX
15
x R
. The units are ppm of FSR
EQ
V
OUT
, where R
50Ω REPRESENTS THE
SPECTRUM ANALYZER
= (2 x I
50Ω
MIN
OUT
EQ
or T
x R
is
EQ
MAX
)V
HSP50415
.
Offset Drift, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance as the temperature is varied from T
T
measured at room temperature to the value measured at
either T
range) per degree
Offset Error, is measured by setting the data inputs to all
logic low (all 0s) and measuring the output voltage through a
known resistance. Offset error is defined as the maximum
deviation of the output current from a value of 0mA.
Output Settling Time, is the time required for the output
voltage to settle to within a specified error band measured
from the beginning of the output transition. The
measurement is done by switching quarter scale.
Termination impedance was 25Ω due to the parallel
resistance of the 50Ω loading on the output and the
oscilloscope’s 50Ω input. This also aids the ability to resolve
the specified error band without overdriving the oscilloscope.
Output Voltage Compliance Range, is the voltage limit
imposed on the output. The output impedance should be
chosen such that the voltage developed does not violate the
compliance range.
Reference Input Multiplying Bandwidth, is defined as the
3dB bandwidth of the voltage reference input. It is measured
by using a sinusoidal waveform as the external reference
with the digital inputs set to all 1s. The frequency is
increased until the amplitude of the output waveform is
0.707 (-3dB) of its original value.
Microprocessor Interface
The HSP50415 is highly configurable with 16
writable/readable control registers and four addresses
reserved for generating internal control signals. The
microprocessor interface (uPI) is a parallel bus type with the
following device pins being used for I/O: CDATA<7:0>,
ADDR<2:0>,
synchronous to the WR pin which is actually the clock for the
uPI logic. Data is written to control words by writing to a
sequence of address locations with the data present on the
CDATA<7:0> bus. The uPI contains a 32-bit master register
which is first loaded with the control word data one byte at a
time, then downloaded to a slave register that is
synchronous to the digital core clock (SYSCLK/2). The
sequence of writes necessary to program control word 12,
for example, with the value 0xAABBCCDD would be as
shown in Table 6 and Figure 20.
MAX
. It is defined as the maximum deviation from the value
MIN
or T
CE
MAX
and RD. These device pins are
o
C.
. The units are ppm of FSR (full scale
April 23, 2007
MIN
FN4559.6
to