HSP50415EVAL1 Intersil, HSP50415EVAL1 Datasheet - Page 16

• Manufacturer Part Number: HSP50415EVAL1
• Description: EVALUATION BOARD HSP50415VI
• Manufacturer: Intersil
• Type: Modulator, Demodulatorr

Specifications of HSP50415EVAL1

• For Use With/related Products: HSP50415
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There should be at least 4 digital core clock cycles between
writing to address 4 and reloading the MasterReg as the
data from the MasterReg is being downloaded to slave
registers synchronous to the core clock cycles and
synchronization circuitry is required. The frequency of the
WR pin may not exceed CLK/4 (25MHz max for CLK of
100MHz). To readback the value in control word 12, the
following sequence of writes/reads shown in Table 7 should
occur. Note that the RD pin is the Three-State control for the
CDATA<7:0> bus with a logic 1 on the RD pin disabling the
output drivers configuring the pins as inputs and a logic 0 on
the RD pin enabling the output drivers making the pins
outputs. The CE pin must be active for any read or write to
the device to be processed. The ADDR<2:0>, CDATA<7:0>
and CE pins when writing to the device (RD=1) are
synchronous to the WR pin, but when reading (RD=0), the
ADDR<2:0> and CE pins are not synchronous to the WR
pin, and are actually mux controls to determine which byte of
the read data is output on the CDATA<7:0> bus.:
ADDR<2:0> CDATA<7:0> CE
TABLE 6. SEQUENCE OF WRITES TO LOAD CNTLWORD12
FIGURE 20. CONTROL REGISTER LOADING SEQUENCE
CDATA<7:0>
0
1
2
3
4
ADDR<2:0>
WR
CE
RD
0xDD
0xCC
0xBB
0xAA
0x0C
DD
0
CC
0
0
0
0
0
1
16
RD WR
1
1
1
1
1
BB
2
1
1
1
1
1
AA
3
write to
MasterReg<7:0>
write to
MasterReg<15:8>
write to
MasterReg<23:16>
write to
MasterReg<31:24>
MasterReg<31:0> ->
cntlWord12<31:0>
OC
OPERATION
4
INTERNAL
X
X
HSP50415
Writing and reading back the internal RAMs require a
different sequence of writes and reads. Each RAM on the
device is accessible through the uPI, with the FIFO only
having readback capability. The user selects which memory
to access and the access type (read or write) as well as the
address mode by programming the memory configuration bits
in ControlWord 0 as shown in Table 8.
Once these bits are programmed, the user loads up the
masterReg<31:0> using the same sequence as shown in
Table 8 followed by a write to internal address 0x0F to
download the masterReg<31:0> data to the internal memory
word buffer. If auto-increment address mode is selected then
the user does not need to provide the memory address for
the data; the address is generated sequentially internal to
the device. If the 64x72-bit RAMs are selected for the
access, then 72-bits of data must be loaded to the internal
memory buffer per memory address. This is accomplished
BIT #
ADDR<2:
4:2
1:0
TABLE 8. CONTROL WORD 0 - MEMORY CONTROL BITS
7
6
5
0>
5
0
1
2
3
VALUE
000
001
010
011
100
101
110
111
00
TABLE 7. READBACK OF CNTLWORD12
0
1
0
1
x
0x0C
0xDD
0xCC
0xBB
0xAA
CDATA<7:
0>
Not Used
Disable Memory Address Auto Increment Mode -
User must provide address
Auto-Increment Memory Address Mode Active
Memory R/W select: Write to Selected Memory
Memory R/W select: Read from Selected Memory
No Memory Access Active
I channel 64x72-bit coefficient RAM selected
Q channel 64x72-bit coefficient RAM selected
I and Q channel 64x72-bit coefficient RAMs
selected for simultaneous access
256x8-bit constellation map RAM selected
256x32-bit FIFO RAM selected
Not Used
Not Used
Memory Word Select Bits <1:0>, load with 00
prior to starting load sequence
0
0
0
0
0
CE
1
0
0
0
0
RD
DEFINITION
1
x
x
x
x
WR
write to addrReg<4:0>
read CntlWord12<7:0>
read
CntlWord12<15:8>
read
CntlWord12<23:16>
read
CntlWord12<31:24>
OPERATION
INTERNAL
April 23, 2007
FN4559.6