PC28F640P33B85A NUMONYX, PC28F640P33B85A Datasheet - Page 43

• Manufacturer Part Number: PC28F640P33B85A
• Description: IC FLASH 64MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F640P33B85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 22b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888226; 888226; PC28F640P33B85; PC28F640P33B85 888226

Numonyx™ StrataFlash
9.0
Table 22: Bus Operations Summary
9.1
9.2
Note:
9.3
November 2007
Order Number: 314749-05
Read
Write
Output Disable
Standby
Reset
Notes:
1.
2.
3.
Bus Operation
Asynchronous
Synchronous
Refer to the
operation.
X = Don’t Care (H or L).
RST# must be at V
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be V
Bus cycles to/from the Numonyx™ StrataFlash
conform to standard microprocessor bus operations.
operations and the logic levels that must be applied to the device control signal inputs.
Read
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
Write
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first.
shows the bus cycle sequence for each of the supported device commands, while
Table 24, “Command Codes and Definitions” on page 46
Section 7.0, “AC Characteristics” on page 29
Write operations with invalid V
should not be attempted.
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Table 23, “Command Bus Cycles” on page 45
®
Embedded Memory (P33)
RST#
SS
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
± 0.2 V to meet the maximum specified power-down current.
Running
CLK
X
X
X
X
X
IH
; CE# must be V
ADV#
X
X
X
L
L
L
CC
and/or V
CE#
H
X
L
L
L
L
IL
Table 23, “Command Bus Cycles” on page 45
).
PP
OE#
H
H
X
X
L
L
voltages can produce spurious results and
for signal-timing details.
®
for valid DQ[15:0] during a write
Embedded Memory (P33) device
WE#
Table 22
H
H
H
X
X
L
describes each command. See
Deasserted
Driven
High-Z
High-Z
High-Z
High-Z
WAIT
summarizes the bus
DQ[15:0]
Output
Output
High-Z
High-Z
High-Z
Input
Datasheet
Notes
2,3
1
2
2
43