PC28F640P33B85A NUMONYX, PC28F640P33B85A Datasheet - Page 63

• Manufacturer Part Number: PC28F640P33B85A
• Description: IC FLASH 64MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F640P33B85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 22b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888226; 888226; PC28F640P33B85; PC28F640P33B85 888226

Numonyx™ StrataFlash
11.4.2
11.4.3
11.4.4
November 2007
Order Number: 314749-05
During a block erase, the WSM executes a sequence of internally-timed events that
conditions, erases, and verifies all bits within the block. Erasing the flash memory array
changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros
only by programming the block.
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR[0] indicates whether the addressed block is erasing. Status
Register bit SR[7] is set upon erase completion.
Status Register bit SR[7] indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR[5] indicates an erase
failure if set. SR[3] set would indicate that the WSM could not perform the erase
operation because V
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 34, “Program Suspend/Resume Flowchart” on page
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. V
while in erase suspend. If RST# is asserted, the device is reset.
Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears SR[7,6]. This command can be written to any address. If status
register error bits are set, the Status Register should be cleared before issuing the next
instruction. RST# must remain deasserted.
Erase Protection
When V
V
PP
is below V
®
Embedded Memory (P33)
PP
= V
Section 7.5, “Program and Erase Characteristics” on page
IL
PPLK
, absolute hardware erase protection is provided for all device blocks. If
PP
, erase operations halt and SR[3] is set indicating a V
must remain at a valid level, and WP# must remain unchanged
PP
was outside of its acceptable limits. SR[1] set indicates that the
70).
39.
PP
-level error.
Datasheet
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