PC28F640P33B85A NUMONYX, PC28F640P33B85A Datasheet - Page 52

• Manufacturer Part Number: PC28F640P33B85A
• Description: IC FLASH 64MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F640P33B85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 22b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888226; 888226; PC28F640P33B85; PC28F640P33B85 888226

Figure 28: Example Latency Count Setting Using Code 3
11.1.0.4
11.1.0.5
Table 28: WAIT Functionality Table (Sheet 1 of 2)
Datasheet
52
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
Synchronous Array Reads
Synchronous Non-Array Reads
A[MAX:0]
D[15:0]
ADV#
CLK
CE#
WAIT Polarity
The WAIT Polarity bit (WP), RCR 10 determines the asserted level (V
When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted
low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted,
OE# asserted, RST# deasserted).
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR 15=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid
on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR 10. See
page
33, and
Condition
Figure 17, “Asynchronous Page-Mode Read Timing” on page
Figure 16, “Asynchronous Single-Word Read (ADV# Latch)” on
0
Code 3
1
High-Z
R103
High-Z
Active
Active
Active
Address
Numonyx™ StrataFlash
2
WAIT
3
®
Embedded Memory (P33)
t
Order Number: 314749-05
Data
OH
Data
or V
4
34.
OL
November 2007
) of WAIT.
Notes
1
1
1
1