PC28F640P33B85A NUMONYX, PC28F640P33B85A Datasheet - Page 55

• Manufacturer Part Number: PC28F640P33B85A
• Description: IC FLASH 64MBIT 85NS 64EZBGA
• Manufacturer: NUMONYX
• Series: StrataFlash™r

Specifications of PC28F640P33B85A

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TBGA
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 85ns
• Interface Type: Parallel/Serial
• Boot Type: Bottom
• Address Bus: 22b
• Operating Supply Voltage (typ): 2.5/3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: EZBGA
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 4M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 888226; 888226; PC28F640P33B85; PC28F640P33B85 888226

Numonyx™ StrataFlash
11.1.0.11
11.1.0.12
11.2
11.2.1
Note:
November 2007
Order Number: 314749-05
Burst Length
The Burst Length bits (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous burst accesses are linear only, and do not wrap within any word length
boundaries (see
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
End of Word Line (EOWL) Considerations
When performing synchronous burst reads with BW set (no wrap) and DH reset (1-
clock cycle), an output “delay” requiring additional clock Wait States may occur when
the burst sequence crosses its first device-row (16-word) boundary. The delay would
take place only once, and will not occur if the burst sequence does not cross a device-
row boundary. The WAIT signal informs the system of this delay when it occurs. If the
burst sequence’s start address is 4-word aligned (i.e. 0x00h, 0x04h, 0x08, 0x0Ch) then
no delay occurs. If the start address is at the end of a 4-word boundary (i.e. 0x03h,
0x07h, 0x0Bh, 0x0Fh), the worst case delay (number of Wait States required) will be
one clock cycle less than the first access Latency Count (LC-1) when crossing the first
device-row boundary (i.e. 0x0Fh to 0x10h). Other address misalignments may require
wait states depending upon the LC setting and the starting address alignment. For
example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but
the same LC setting of 3 with a starting address of 0xFE would require 1 wait state
when crossing the first device row boundary.
Read Operations
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read Query. Upon power-up, or after a reset, the device defaults to Read Array
mode. To change the read state, the appropriate read command must be written to the
device (see
sections describe read-mode operations in detail.
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The RCR must be configured to enable synchronous burst reads of the flash
memory array (see
register. It functions independent of VPP. The WSM sets and clears SR[7,6,2], but it
sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before
starting a command sequence to avoid any ambiguity. A device reset also clears the
Status Register.Read Configuration Register” on page
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to Read Array mode. However, to perform array reads after
any other device operation (e.g. write operation), the Read Array command must be
issued in order to read from the flash memory array.
Asynchronous page-mode reads can only be performed when RCR 15 is set
The Clear Status Register command clears the status register. It functions independent
of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing
them. The Status Register should be cleared before starting a command sequence to
avoid any ambiguity. A device reset also clears the Status Register.
®
Embedded Memory (P33)
Section 9.6, “Device Command Bus Cycles” on page
Table 29, “Burst Sequence Word Ordering” on page
Section , “The Clear Status Register command clears the status
49).
44). The following
54). When a burst
Datasheet
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