ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 15

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(OR) is set high once RESETN is pulled low, and remains
in that state until calibration is complete. The OR output
returns to normal operation at that time, so it is
important that the analog input be within the converter’s
full-scale range to observe the transition. If the input is in
an over-range condition the OR pin will stay high, and it
will not be possible to detect the end of the calibration
cycle.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 500MSPS
the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
User Initiated Reset
Recalibration of the A/D can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength in its
high impedance state of less than 0.5mA is
recommended, as RESETN has an internal high
impedance pull-up to OVDD. As is the case during
power-on reset, the SDO, RESETN and DNC pins must be
in the proper state for the calibration to successfully
execute.
The performance of the ISLA112P50 changes with
variations in temperature, supply voltage or sample rate.
The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the A/D under the environmental conditions
at which it will operate.
A supply voltage variation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less
than 80MSPS will typically result in an SNR change of
less than 0.5dBFS and an SFDR change of less than
3dBc.
Figures 27 and 28 show the effect of temperature on
SNR and SFDR performance with power on calibration
performed at -40°C, +25°C, and +85°C. Each plot shows
CLKOUTP
RESETN
CLKN
CLKP
ORP
FIGURE 26. CALIBRATION TIMING
CALIBRATION
BEGINS
15
CALIBRATION
CALIBRATION
COMPLETE
TIME
ISLA112P50
the variation of SNR/SFDR across temperature after a
single power on calibration at -40°C, +25°C and +85°C.
Best performance is typically achieved by a user-initiated
power on calibration at the operating conditions, as
stated earlier. However, it can be seen that performance
drift with temperature is not a very strong function of the
temperature at which the power on calibration is
performed. To achieve the performance demonstrated in
the SFDR plot, I2E must be in Track mode.
Analog Input
A single fully differential input (VINP/VINN) connects to
the sample and hold amplifier (SHA) of each unit A/D.
The ideal full-scale input voltage is 1.45V, centered at the
VCM voltage of 0.535V as shown in Figure 29.
FIGURE 27. SNR PERFORMANCE vs TEMPERATURE
FIGURE 28. SFDR PERFORMANCE vs TEMPERATURE
-1
-2
-3
-4
-10
-15
3
2
1
0
15
10
-40
-5
5
0
-40
FIGURE 29. ANALOG INPUT RANGE
1.8
1.4
1.0
0.6
0.2
AFTER +25°C CALIBRATION
AFTER +25°C CALIBRATION
-15
-15
CAL DONE AT
CAL DONE AT
0.725V
-40°C
CAL DONE AT
TEMPERATURE (°C)
CAL DONE AT
-40°C
TEMPERATURE (°C)
10
+85°C
+85°C
10
INP
35
35
CAL DONE AT
+25°C
CAL DONE AT
+25°C
60
60
INN
VCM
0.535V
June 17, 2010
FN7604.1
85
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