ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 26

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

value + hysteresis to again enter the Track state. The
hysteresis quantity is a 24-bit value, constructed with bits
23 through 12 (MSBs) being assigned to 0, bits 11 through
4 assigned to this register’s value, and bits 3 through 0
(LSBs) assigned to 0.
ADDRESS 0X60-0X64: I2E INITIALIZATION
These registers provide access to the initialization values
for each of offset, gain, and sample time skew that I2E
programs into the target core A/D before adjusting to
minimize interleave mismatch. They can be used by the
system to, for example, reduce the convergence time of
the I2E algorithm by programming in the optimal values
before turning I2E on. In this case, I2E only needs to
adjust for temperature and voltage-induced changes
since the optimal values were recorded.
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing
skew between the two A/D cores. The nominal range and
resolution of this adjustment are given in Table 10. The
default value of this register after power-up is 80h.
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the
A/D input sample clock. Some systems with multiple A/Ds
can more easily latch the data from each A/D by controlling
the phase of the output data clock. This control is
accomplished through the use of the phase_slip SPI
feature, which allows the rising edge of the output data
clock to be advanced by one input clock period, as shown in
the Figure 44. Execution of a phase_slip command is
accomplished by first writing a '0' to bit 0 at address 0x71,
followed by writing a '1' to bit 0 at address 0x71.
Clock (500MHz)
Clock (250MHz)
Clock (250MHz)
Clock (250MHz)
No clock_slip
Output Data
Output Data
1 clock_slip
2 clock_slip
Output Data
ADC Input
TABLE 10. DIFFERENTIAL SKEW ADJUSTMENT
–Full Scale (0x00)
+Full Scale (0xFF)
Nominal Step Size
Mid–Scale (0x80)
PARAMETER
Steps
FIGURE 44. PHASE SLIP
2ns
2ns
26
DIFFERENTIAL SKEW
0x70[7:0]
+6.5ps
-6.5ps
4ns
0.0ps
51fs
256
ISLA112P50
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
ISLA112P50 can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 17). This functionality can be overridden and
controlled through the SPI, as shown in Table 11.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to
“Data Format” on page 18). This functionality can be
overridden and controlled through the SPI, as shown in
Table 12.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
Internal clock signals are generated by a delay-locked
loop (DLL), which has a finite operating range. Table 13
shows the allowable sample rate ranges for the slow and
fast settings.
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock generator. The method
DLL RANGE
This bit sets the DLL operating range to fast (default)
or slow.
Slow
Fast
TABLE 12. OUTPUT FORMAT CONTROL
TABLE 11. OUTPUT MODE CONTROL
VALUE
VALUE
000
001
010
100
000
001
010
100
TABLE 13. DLL RANGES
MIN
160
80
MAX
200
500
OUTPUT FORMAT
Two’s Complement
OUTPUT MODE
Offset Binary
0x93[2:0]
Pin Control
Gray Code
0x93[7:5]
Pin Control
LVDS 2mA
LVDS 3mA
LVCMOS
June 17, 2010
UNIT
MSPS
MSPS
FN7604.1