ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 24

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation, nap or sleep modes (refer to“Nap/Sleep” on
page 17). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
ADDRESS 0X30: I2E STATUS
The I2E general status register.
Bits 0 and 1 indicate if the I2E circuitry is in Active Run or
Hold state. The state of the I2E circuitry is dependent on
the analog input signal itself. If the input signal obscures
the interleave mismatched artifacts such that I2E cannot
estimate the mismatch, the algorithm will dynamically
enter the Hold state. For example, a DC mid-scale input
to the A/D does not contain sufficient information to
estimate the gain and sample time skew mismatches,
and thus the I2E algorithm will enter the Hold state. In
the Hold state, the analog adjustments for interleave
correction will be frozen and mismatch estimate
calculations will cease until such time as the analog input
+Full Scale (0xFF)
–Full Scale (0x00)
Nominal Step Size
Mid–Scale (0x80)
TABLE 8. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x22[3:0]
Steps
Bit3
Bit2
Bit1
Bit0
TABLE 7. COARSE GAIN ADJUSTMENT
TABLE 9. POWER-DOWN CONTROL
VALUE
000
001
010
100
NOMINAL COARSE GAIN ADJUST
MEDIUM GAIN
0x23[7:0]
0.016%
0.00%
24
+2%
-2%
256
POWER DOWN MODE
Normal Operation
(%)
+2.8
+1.4
-2.8
-1.4
Sleep Mode
0x25[2:0]
Pin Control
Nap Mode
FINE GAIN
0x24[7:0]
0.0016%
-0.20%
+0.2%
0.00%
256
ISLA112P50
achieves sufficient quality to allow the I2E algorithm to
make mismatch estimates again.
Bit 0: 0 = I2E has not detected a low power condition.
1 = I2E has detected a low power condition, and the
analog adjustments for interleave correction are frozen.
Bit 1: 0 = I2E has not detected a low AC power
condition. 1 = I2E has detected a low AC power
condition, and I2E will continue to correct with best
known information but will not update its interleave
correction adjustments until the input signal achieves
sufficient AC RMS power.
Bit 2: When first started, the I2E algorithm can take a
significant amount of time to settle (~1s), dependent on
the characteristics of the analog input signal. 0 = I2E is
still settling, 1 = I2E has completed settling.
ADDRESS 0X31: I2E CONTROL
The I2E general control register. This register can be
written while I2E is running to control various
parameters.
Bit 0: 0 = turn I2E off, 1= turn I2E on
Bit 1: 0 = no action, 1 = freeze I2E, leaving all settings
in the current state. Subsequently writing a 0 to this bit
will allow I2E to continue from the state it was left in.
Bit 2-4: Disable any of the interleave adjustments of
offset, gain, or sample time skew
Bit 5: 0 = bypass notch filter, 1 = use notch filter on
incoming data before estimating interleave mismatch
terms
ADDRESS 0X32: I2E STATIC CONTROL
The I2E general static control register. This register must
be written prior to turning I2E on for the settings to take
effect.
Bit 1-4: Reserved, always set to 0
Bit 5: 0 = normal operation, 1 = skip coarse adjustment
of the offset, gain, and sample time skew analog controls
when I2E is first turned on. This bit would typically be
used if optimal analog adjustment values for offset, gain,
and sample time skew have been preloaded in order to
have the I2E algorithm converge more quickly.
The system gain of the pair of interleaved core A/Ds can
be set by programming the medium and fine gain of the
reference A/D before turning I2E on. In this case, I2E will
adjust the non-reference A/D’s gain to match the
reference A/D’s gain.
Bit 7: Reserved, always set to 0
ADDRESS 0X4A: I2E POWER DOWN
This register provides the capability to completely power
down the I2E algorithm and the Notch filter. This would
typically be done to conserve power.
BIT 0: Power down the I2E Algorithm
BIT 1: Power down the Notch Filter
June 17, 2010
FN7604.1