ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 28

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Memory Map
ADDR
(Hex)
03-07
11-1F
26-2F
33-49
4B-4F
53-54
00
01
02
08
09
10
20
21
22
23
24
25
30
31
32
4A
50
51
52
I2E Power Down
Threshold MSBs
device_index_A
Threshold LSBs
I2E RMS Power
I2E RMS Power
PARAMETER
gain_medium
offset_coarse
chip_version
gain_coarse
port_config
I2E Control
offset_fine
I2E Status
Hysteresis
burst_end
I2E Static
gain_fine
reserved
reserved
reserved
reserved
reserved
reserved
I2E RMS
reserved
chip_id
Control
NAME
modes
28
Reserved
must be
set to 0
(MSB)
BIT 7
Active
SDO
BIT 6
First
LSB
Reserved
TABLE 15. SPI MEMORY MAP
adjustment
Reserved
Enable
coarse
BIT 5
Reset
notch
filter
Soft
Skip
RMS Power Threshold, MSBs
RMS Power Threshold, LSBs
Reserved
ISLA112P50
Burst end address [7:0]
RMS Power Hysteresis
Chip Version #
Coarse Offset
Medium Gain
Disable
BIT 4
Fine Offset
Offset
Chip ID #
Fine Gain
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved, must be set to 0
Disable
BIT 3
Gain
Disable
Settled
001 = Normal Operation
Other codes = Reserved
BIT 2
Mirror
(bit5)
Skew
Coarse Gain
I2E
Power-Down Mode
000 = Pin Control
100 = Sleep
010 = Nap
Low AC
ADC01
Freeze
BIT 1
Mirror
[2:0]
Power
Power
(bit6)
Notch
Down
Filter
RMS
ADC00
(LSB)
BIT 0
Power
Power
Mirror
(bit7)
Down
RMS
Low
Run
I2E
Read only
Read only
Read only
cal. value
cal. value
cal. value
cal. value
cal. value
affected
VALUE
(Hex)
Reset
DEF.
NOT
Soft
00h
00h
00h
00h
20h
00h
00h
00h
10h
FFh
by
June 17, 2010
INDEXED
/GLOBAL
FN7604.1
G
G
G
G
G
G
G
G
G
G
G
G
G
G
I
I
I
I
I
I
I
I