ISLA112P50IR72EV1Z Intersil, ISLA112P50IR72EV1Z Datasheet - Page 32

• Manufacturer Part Number: ISLA112P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA112P50IR73
• Manufacturer: Intersil

Specifications of ISLA112P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A/D Evaluation Platform
Intersil offers an A/D Evaluation platform which can be
used to evaluate any of Intersil’s high speed A/D
products. The platform consists of a FPGA based data
capture motherboard and a family of A/D daughtercards.
This USB based platform allows a user to quickly
evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
http://www.intersil.com/converters/adc_eval_platform/
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex
board designs benefit from isolating the analog and
digital sections. Analog supply and ground planes should
be laid out under signal and clock inputs. Locate the
digital planes under outputs and logic pins. Grounds
should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs
for the analog input and clock signals. Locate
transformers and terminations as close to the chip as
possible.
Exposed Paddle
The exposed paddle must be electrically connected to
analog ground (AVSS) and should be connected to a
large copper plane using numerous vias for optimal
thermal performance.
Bypass and Filtering
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close
to device pins. Longer traces will increase inductance,
resulting in diminished dynamic performance and
accuracy. Make sure that connections to ground are
direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be operated do not require connection to
ensure optimal A/D performance. These inputs can be
left floating if they are not used. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT) accept a floating input as a valid
state, and therefore should be biased according to the
desired functionality.
32
ISLA112P50
Definitions
Analog Input Bandwidth is the analog input frequency
at which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Aperture Delay or Sampling Delay is the time
required after the rise of the clock input for the sampling
switch to open, at which time the signal is held for
conversion.
Aperture Jitter is the RMS variation in aperture delay
for a set of samples.
Clock Duty Cycle is the ratio of the time the clock wave
is at logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of
any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate
method of specifying Signal to Noise-and-Distortion Ratio
(SINAD). In dB, it is calculated as: ENOB = (SINAD -
1.76)/6.02
Gain Error is the ratio of the difference between the
voltages that cause the lowest and highest code
transitions to the full-scale voltage less 2 LSB. It is
typically expressed in percent.
I2E The Intersil Interleave Engine. This highly
configurable circuitry performs estimates of offset, gain,
and sample time skew mismatches between the core
converters, and updates analog adjustments for each to
minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum
deviation of the A/D’s transfer function from a best fit line
determined by a least squares curve fit of that transfer
function, measured in units of LSBs.
Least Significant Bit (LSB) is the bit that has the
smallest value or weight in a digital word. Its value in
terms of input voltage is V
resolution in bits.
Missing Codes are output codes that are skipped and
will never appear at the A/D output. These codes cannot
be reached with any input value.
Most Significant Bit (MSB) is the bit that has the
largest value or weight.
Pipeline Delay is the number of clock cycles between
the initiation of a conversion and the appearance at the
output pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of
the observed magnitude of a spur in the A/D FFT, caused
by an AC signal superimposed on the power supply
voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one half the clock frequency,
including harmonics but excluding DC.
FS
/(2
N
-1) where N is the
June 17, 2010
FN7604.1