LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 38

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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SETUP REGISTERS
SLEEP STATE CONTROL AND MASK REGISTERS
OTHER MASK REGISTERS
ZONE 1 AND 2 TEMPERATURE READING OFFSET REGISTERS
16.0 Registers
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Zone 1 Base Temperature
Zone 2 Base Temperature
Zone 3 Base Temperature
Zone 4 Base Temperature
Step 2 Temp Offset
Step 3 Temp Offset
Step 4 Temp Offset
Step 5 Temp Offset
Step 6 Temp Offset
Step 7 Temp Offset
Step 8 Temp Offset
Step 9 Temp Offset
Step 10 Temp Offset
Step 11 Temp Offset
Step 12 Temp Offset
Step 13 Temp Offset
Special Function TACH to PWM
Binding
Reserved
LM93 Status/Control
LM93 Configuration
Sleep State Control
S1 GPI Mask
S1 Fan Mask
S3 GPI Mask
S3 Fan Mask
S3 Temperature/Voltage Mask
S4/5 GPI Mask
S4/5 Temperature/Voltage Mask
GPI Error Mask
Miscellaneous Error Mask
Special Function Zone 1 Adjustment
Offset
Special Function Zone 2 Adjustment
Offset
Register Name
(Continued)
Address Default
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h
E1
E2h
E3h
E4h
E5h
E6h
E7h
E8h
E9h
EAh
EBh
ECh
EDh
EEh
EFh
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
N/D
00h
N/D
00h
00h
03h
FFh
0Fh
FFh
0Fh
07h
FFh
07h
FFh
3Fh
00h
00h
38
Base temperature to which look-up table offset is applied for
Zone 1
Base temperature to which look-up table offset is applied for
Zone 2
Base temperature to which look-up table offset is applied for
Zone 3
Base temperature to which look-up table offset is applied for
Zone 4
Step 2 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 3 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 4 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 5 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 6 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 7 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 8 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 9 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 10 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 11 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 12 Zone 1/2 and Zone 3/4 Offset Temperatures
Step 13 Zone 1/2 and Zone 3/4 Offset Temperatures
Controls the tachometer input to PWM output binding
Gives Master error status, ASF reset control and Max PWM
control
Configures various outputs and provides START bit
Used to communicate the system sleep state to the LM93
Sleep state S1 GPI error mask register
Sleep state S1 fan tach error mask register
Sleep state S3 GPI error mask register
Sleep state S3 fan tach error mask register
Sleep state S3 temperature or voltage error mask register
Sleep state S4/5 GPI error mask register
Sleep state S4/5 temperature or voltage error mask register
Error mask register for GPI faults
Error mask register for VRDx_HOT, SCSI_TERMx, and
dynamic Vccp limit checking.
Allows all Zone 1 temperature measurements to be adjusted by
a programmable offset
Allows all Zone 2 temperature measurements to be adjusted by
a programmable offset
Description