LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 77

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register
Address
16.0 Registers
16.8.23 Register E0h Special Function TACH to PWM Binding
If a TACH channel is bound to a PWM channel, TACH errors on that channel are automatically masked when the bound PWM
is at 0% duty cycle or performing spin-up. Behavior is undefined if a TACH channel is bound to both PWM outputs. This register
must be setup when Smart Tach Mode is enabled in register BDh, Special Function Control 2.
E0h
Read/
Write
R/W
Bit
0
1
2
3
4
5
6
7
Special Function
TACH to PWM
(Continued)
Register
Binding
Name
Name
T1P1
T1P2
T2P1
T2P2
T3P1
T3P2
T4P1
T4P2
T4P2
Bit 7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
T4P1
Bit 6
If set, TACH1 is bound to PWM1.
If set, TACH1 is bound to PWM2.
If set, TACH2 is bound to PWM1.
If set, TACH2 is bound to PWM2.
If set, TACH3 is bound to PWM1.
If set, TACH3 is bound to PWM2.
If set, TACH4 is bound to PWM1.
If set, TACH4 is bound to PWM2.
T3P2
77
Bit 5
T3P1
Bit 4
Description
T2P2
Bit 3
T2P1
Bit 2
T1P2
Bit 1
T1P1
Bit 0
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Default
Value
00h