LM93CIMT National Semiconductor, LM93CIMT Datasheet - Page 82

• Manufacturer Part Number: LM93CIMT
• Description: Microprocessor Support IC
• Manufacturer: National Semiconductor

Specifications of LM93CIMT

• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 3.6V
• Leaded Process Compatible: No
• Supply Voltage Min: 3V
• Operating Temperature Min: 0��C
• Package / Case: 56-TSSOP
• Operating Temperature Max: 85°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Register
Address
Register
Address
Register
Address
16.0 Registers
16.9.4 Register E7h S3 GPI Mask
16.9.5 Register E8h S3 Tach Mask
16.9.6 Register E9h S3 Temperature/Voltage Mask
E7h
E8h
E9h
Read/
Write
R/W
Read/
Write
Read/
Write
R/W
R/W
7:4
Register
Bit
S3 GPI
0
1
2
3
Name
7:3
Bit
Bit
Register
Mask
S3 Tach
0
1
2
3
4
5
6
7
S3 Voltage
0
1
2
3
Name
Register
Mask
Name
Mask
TACH1_S3_MSK
TACH2_S3_MSK
TACH3_S3_MSK
TACH4_S3_MSK
AIN12_S3_MSK
AIN13_S3_MSK
AIN14_S3_MSK
TEMP_S3_MSK
GPI0_S3_MSK
GPI1_S3_MSK
GPI2_S3_MSK
GPI3_S3_MSK
GPI4_S3_MSK
GPI5_S3_MSK
GPI6_S3_MSK
GPI7_S3_MSK
(Continued)
GPI7_S3
Name
Name
Name
_MSK
RES
RES
Bit 7
Bit 7
Bit 7
Bit 6
GPI6_S3
_MSK
Bit 6
Bit 6
RES
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
RES
Bit 5
R
Bit 5
GPI5_S3
_MSK
Bit 5
If set, GPI0 errors are masked in S3 sleep state.
If set, GPI1 errors are masked in S3 sleep state.
If set, GPI2 errors are masked in S3 sleep state.
If set, GPI3 errors are masked in S3 sleep state.
If set, GPI4 errors are masked in S3 sleep state.
If set, GPI5 errors are masked in S3 sleep state.
If set, GPI6 errors are masked in S3 sleep state.
If set, GPI7 errors are masked in S3 sleep state.
If set, AIN12 errors as masked in S3 sleep state.
If set, AIN13 errors as masked in S3 sleep state.
If set, AIN14 errors as masked in S3 sleep state.
If set, temperature errors and diode fault errors for
zones 1 and 2 are masked in S3 sleep state.
Reserved
Bit 4
If set, Tach1 errors are masked in S3 sleep state.
If set, Tach2 errors are masked in S3 sleep state.
If set, Tach3 errors are masked in S3 sleep state.
If set, Tach4 errors are masked in S3 sleep state.
Reserved
Bit 4
82
GPI4_S3
TACH4_S3
_MSK
Bit 4
_MSK
Bit 3
S3_MSK
TEMP_
Bit 3
GPI3_S3
Description
Description
_MSK
Description
Bit 3
TACH3_S3
AIN14_S3
_MSK
Bit 2
_MSK
Bit 2
GPI2_S3
_MSK
Bit 2
TACH2_S3
AIN13_S3
_MSK
Bit 1
_MSK
Bit 1
GPI1_S3
_MSK
Bit 1
TACH1_S3
AIN12_S3
_MSK
_MSK
GPI0_S3
Bit 0
Bit 0
_MSK
Bit 0
Default
Default
Default
Value
Value
Value
07h
0Fh
FFh