PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 20

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F7X7
2.2.2
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
DS30498C-page 18
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’, r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> bits, whose contents
Bank 0
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
2: Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices (except for RE3), read as ‘0’.
6: This bit always reads as a ‘1’.
7: OSCCON<OSTS> bit resets to ‘0’ with dual-speed start-up and LP, HS or HS-PLL selected as the oscillator.
8: RE3 is an input only. The state of the TRISE3 bit has no effect and will always read ‘1’.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRESH
ADCON0
Shaded locations are unimplemented, read as ‘0’.
are transferred to the upper byte of the program counter during branches (CALL or GOTO).
SPECIAL FUNCTION REGISTERS
Name
SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
Timer0 Module Register
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
AUSART Transmit Data Register
AUSART Receive Data Register
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
A/D Result Register High Byte
PSPIF
ADCS1
OSFIF
WCOL
SPEN
Bit 7
IRP
GIE
—
—
—
—
—
—
(3)
TOUTPS3 TOUTPS2
T1RUN
SSPOV
ADCS0
CMIF
Bit 6
PEIE
ADIF
RP1
RX9
—
—
—
—
T1CKPS1
TMR0IE
SSPEN
CCP1X
CCP2X
LVDIF
SREN
CHS2
RCIF
Bit 5
RP0
—
—
Write Buffer for the upper 5 bits of the Program Counter
TOUTPS1
T1CKPS0
CCP1Y
CCP2Y
INT0IE
CREN
CHS1
Bit 4
TXIF
CKP
TO
—
—
T1OSCEN T1SYNC
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
CCP1M3
CCP2M3
SSPM3
ADDEN
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
SSPIF
BCLIF
CHS0
RBIE
Bit 3
RE3
PD
GO/DONE
CCP1M2
CCP2M2
TMR0IF
CCP1IF
SSPM2
FERR
Bit 2
RE2
—
Z
TMR1CS TMR1ON -000 0000
CCP1M1 CCP1M0 --00 0000
CCP2M1 CCP2M0 --00 0000
TMR2IF
CCP3IF
SSPM1
INT0IF
OERR
CHS3
Bit 1
RE1
DC
 2004 Microchip Technology Inc.
TMR1IF
CCP2IF
SSPM0
ADON
RX9D
RBIF
Bit 0
RE0
C
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xx0x 0000
xx00 0000
xxxx xxxx
xxxx xxxx
---- x000
---0 0000
0000 000x
0000 0000
000- 0-00
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx 101, 180
0000 0000 101, 180
xxxx xxxx
xxxx xxxx
0000 000x 134, 180
0000 0000 139, 180
0000 0000 141, 180
xxxx xxxx
xxxx xxxx
xxxx xxxx 160, 180
0000 0000 152, 180
POR, BOR
Value on:
on page
30, 180
76, 180
29, 180
21, 180
30, 180
55, 180
64, 180
66, 180
67, 180
68, 180
29, 180
23, 180
25, 180
27, 180
83, 180
83, 180
83, 180
86, 180
86, 180
90, 180
90, 180
88, 180
92, 180
92, 180
88, 180
Details