PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 27

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.2.5
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5:
 2004 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR1 Register
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ADDRESS 0Ch)
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion is completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: AUSART Receive Interrupt Flag bit
1 = The AUSART receive buffer is full
0 = The AUSART receive buffer is empty
TXIF: AUSART Transmit Interrupt Flag bit
1 = The AUSART transmit buffer is empty
0 = The AUSART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred and must be cleared in software before returning
0 = No SSP interrupt condition has occurred
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
-n = Value at POR
bit 7
PSPIF
R/W-0
Note:
from the Interrupt Service Routine. The conditions that will set this bit are:
SPI:
A transmission/reception has taken place.
I
A transmission/reception has taken place.
I
A transmission/reception has taken place. The initiated Start condition was completed by
the SSP module. The initiated Stop condition was completed by the SSP module. The
initiated Restart condition was completed by the SSP module.The initiated Acknowledge
condition was completed by the SSP module. A Start condition occurred while the SSP
module was Idle (multi-master system). A Stop condition occurred while the SSP module
was Idle (multi-master system).
2
2
C Slave:
C Master:
(1)
PSPIF is reserved on 28-pin devices; always maintain this bit clear.
R/W-0
ADIF
RCIF
R-0
W = Writable bit
‘1’ = Bit is set
TXIF
R-0
Note: Interrupt flag bits are set when an interrupt
SSPIF
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
software should ensure the appropriate inter-
condition occurs regardless of the state of its
corresponding enable bit or the Global Inter-
rupt Enable bit, GIE (INTCON<7>). User
rupt bits are clear prior to enabling an interrupt.
(1)
CCP1IF
R/W-0
PIC16F7X7
x = Bit is unknown
TMR2IF
R/W-0
DS30498C-page 25
TMR1IF
R/W-0
bit 0