PIC16F767-E/ML Microchip Technology, PIC16F767-E/ML Datasheet - Page 87

• Manufacturer Part Number: PIC16F767-E/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.0
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable and is cleared on any device
Reset.
The input clock (F
1:4
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon Reset.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt, latched in flag bit,
TMR2IF (PIR1<1>).
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Register 8-1 shows the Timer2 Control register.
Additional information on timer modules is available in
the “PICmicro
Manual” (DS33023).
 2004 Microchip Technology Inc.
or
TIMER2 MODULE
1:16,
®
Mid-Range MCU Family Reference
OSC
selected
/4) has a prescale option of 1:1,
by
control
bits,
8.1
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device Reset (POR, MCLR Reset, WDT
TMR2 is not cleared when T2CON is written.
8.2
The output of TMR2 (before the postscaler) is fed to the
SSP module which optionally uses it to generate the
shift clock.
FIGURE 8-1:
Reset or BOR)
Note 1: TMR2 register output can be software selected by the
Sets Flag
bit TMR2IF
1:1 to 1:16
Postscaler
TOUTPS3:
TOUTPS0
Timer2 Prescaler and Postscaler
Output of TMR2
SSP module as a baud clock.
4
TMR2
Output
Reset
EQ
(1)
Comparator
TMR2 Reg
PR2 Reg
TIMER2 BLOCK DIAGRAM
PIC16F7X7
1:1, 1:4, 1:16
Prescaler
DS30498C-page 85
T2CKPS1:
T2CKPS0
2
F
OSC
/4