S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 209

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

2: INTERFACING TO THE MOTOROLA MPC821 MICROPROCESSOR
2 I
2.1 Introduction
2.2 Interfacing to the MPC821
The MPC8xx System Bus
MPC821 Bus Overview
5-8
MPC821 M
This application note describes the hardware and software environment required to interface the
S1D13705 Embedded Memory LCD Controller and the Motorola MPC821 Processor.
The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern
RISC microprocessors. This section provides an overview of the operation of the CPU bus in order
to establish interface requirements.
The MPC8xx microprocessor family uses a synchronous address and data bus. All IO is
synchronous to a square-wave reference clock called MCLK (Master Clock). This clock runs at the
machine cycle speed of the CPU core (typically 25 to 50 MHz). Most outputs from the processor
change state on the rising edge of this clock. Similarly, most inputs to the processor are sampled on
the rising edge.
Note: The external bus can run at one-half the CPU core speed using the clock control register. This
The MPC821 can generate up to eight independent chip select outputs, each of which may be
controlled by one of two types of timing generators: the General Purpose Chip Select Module
(GPCM) or the User-Programmable Machine (UPM). Examples are given using the GPCM.
It should be noted that all Power PC microprocessors, including the MPC8xx family, use bit notation
opposite from the convention used by most other microprocessor systems. Bit numbering for the
MPC8xx always starts with zero as the most significant bit, and increments in value to the least-
significant bit. For example, the most significant bits of the address bus and data bus are A0 and D0,
while the least significant bits are A31 and D31.
The MPC8xx uses both a 32-bit address and data bus. A parity bit is supported for each of the four
byte lanes on the data bus. Parity checking is done when data is read from external memory or
peripherals, and generated by the MPC8xx bus controller on write cycles. All IO accesses are
memory-mapped meaning there is no separate IO space in the Power PC architecture.
Support is provided for both on-chip (DMA controllers) and off-chip (other processors and
peripheral controllers) bus masters.
The bus can support both normal and burst cycles. Burst memory cycles are used to fill
on-chip cache memory, and for certain on-chip DMA operations. Normal cycles are used for all
other data transfers.
X27A-G-010-01
NTERFACING TO THE
is typically used when the CPU core is operated above 50 MHz.
ICROPROCESSOR
EPSON
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OTOROLA
S1D13705F00A APPLICATION NOTES
(X27A-G-010-01)