S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 63

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

8: REGISTERS
1-54
REG[1Bh] Portrait Mode Register
Address = 1FFFBh
Portrait Mode
Enable
bit 7
bit 6
bit 2
bits 1-0
Portrait Mode
Select
Portrait Mode Enable
When this bit = 1, Portrait Mode is enabled. When this bit = 0, Landscape Mode is
enabled.
Portrait Mode Select
When this bit = 0, Default Portrait Mode is selected. When this bit = 1, Alternate Portrait
Mode is selected. See Section 12 “SwivelView Mode” on page 1-64 for further informa-
tion on Portrait Mode.
The following table shows the selection of Portrait Mode.
reserved
reserved bits must be set to 0.
Portrait Mode Pixel Clock Select Bits [1:0]
These two bits select the Pixel Clock (PCLK) source in Portrait Mode - these bits have no
effect in Landscape Mode. The following table shows the selection of PCLK and MCLK
in Portrait Mode - see Section 12 “SwivelView Mode” on page 1-64 for details.
(REG[1Bh] bit 7)
(REG[1Bh] bit 7)
Portrait Mode
Portrait Mode
Enable
Enable
0
1
1
1
1
1
1
1
1
0
1
1
n/a
(REG[1Bh] bit 6)
Portrait Mode
(REG[1Bh] bit 6)
Portrait Mode
Select
Table 8-8 Selection of PCLK and MCLK in Portrait Mode
Select
X
0
0
0
0
1
1
1
1
X
Table 8-7 Selection of Portrait Mode
0
1
n/a
Where CLK is CLKI (REG[02h] bit 4 = 0) or CLKI/2 (REG[02h] bit 4 = 1)
Pixel Clock (PCLK) Select
EPSON
Bit 1
(REG[1Bh] bits [1:0]
X
0
0
1
1
0
0
1
1
n/a
Bit 0
Alternate Portrait
X
0
1
0
1
0
1
0
1
Default Portrait
Landscape
Mode
reserved
S1D13705F00A HARDWARE FUNCTIONAL
PCLK =
CLK/2
CLK/4
CLK/8
CLK/2
CLK/2
CLK/4
CLK/8
CLK
CLK
SPECIFICATION (X27A-A-001-06)
Portrait Mode
Pixel Clock
Select Bit 1
See Reg[02h] bit 5
MCLK =
Portrait Mode
CLK/2
CLK/4
CLK/8
CLK/2
CLK/4
Pixel Clock
Select Bit 0
CLK
CLK
CLK
Read/Write