S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 221

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

3: INTERFACING TO THE MOTOROLA MCF5307 “COLDFIRE” MICROPROCESSOR
Burst Cycles
Chip-Select Module
3.3 S1D13705 Bus Interface
Host Bus Pin Connection
5-20
Burst cycles are very similar to normal cycles, except that they occur as a series of four back-to-
back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output asserted
continuously through the burst. Burst memory cycles are mainly intended to facilitate cache line fill
from program or data memory; they are typically not used for transfers to or from IO peripheral
devices such as the S1D13705. The MCF5307 chip selects provide a mechanism to disable burst
accesses for peripheral devices which are not able to support them.
In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select Module
can generate active-low Output Enable (OE) and Write Enable (BWE) signals compatible with most
memory and x86-style peripherals. The MCF5307 bus controller also provides a Read/Write (R/W)
signal which is compatible with most 68K peripherals.
Chip selects 0 and 1 can be programmed independently to respond to any base address and block
size. Chip select 0 can be active immediately after reset, and is typically used to control a boot
ROM. Chip select 1 is likewise typically used to control a large static or dynamic RAM block.
Chip selects 2 through 7 have fixed block sizes of 2M bytes each. Each has a unique, fixed offset
from a common, programmable starting address. These chip selects are well-suited to typical IO
addressing requirements.
Each chip select may be individually programmed for port size (8/16/32 bits), 0 to 15 wait states or
external acknowledge, address space type, burst or non-burst cycle support, and write protect.
This section is a summary of the host bus interface mode used on the S1D13705 to interface to the
MCF5307.
The S1D13705 implements a 16-bit interface to the host microprocessor which may operate in one
of several modes compatible with most of the popular embedded microprocessor families. The
interface mode used for the MCF5307 is:
• Generic #1 (Chip Select, plus individual Read Enable/Write Enable for each byte).
For details on configuration, refer to the “S1D13705 Hardware Functional Specification”,
document number X27A-A-001-02.
Table 3-1 Host Bus Interface Pin Mapping
Pin Names
S1D13705
AB[15:1]
DB[15:0]
RD/WR#
RESET#
WAIT#
BCLK
WE1#
WE0#
AB0
RD#
CS#
BS#
EPSON
External Decode
connect to V
Generic #1
RESET#
A[15:1]
D[15:0]
WAIT#
BCLK
WE1#
WE0#
RD1#
RD0#
A0
SS
S1D13705F00A APPLICATION NOTES
(X27A-G-011-01)