S1D15206F00A200 Epson, S1D15206F00A200 Datasheet - Page 220

• Manufacturer Part Number: S1D15206F00A200
• Description: LCD Drivers LCD DRIVER
• Manufacturer: Epson

Specifications of S1D15206F00A200

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The 65 rows are divided into 8 pages of 8 lines and a ninth
page with a single line (D0 only). Data is read from or
written to the 8 lines of each page directly through D0 to
D7.
The microprocessor reads from and writes to RAM
through the I/O buffer. Since the LCD controller oper-
ates independently, data can be written to RAM at the
same time as data is being displayed, without causing the
LCD to flicker.
Column Address Counter
The column address counter is an 8-bit presettable coun-
ter that provides the column address to display data
RAM. See figure 4. It is incremented by 1 each time a
read or write command is received. The counter auto-
matically stops at the highest address, A6H. The con-
tents of the column address counter are changed by the
Column Address Set command. This counter is inde-
pendent of the page address register.
When the Select ADC command is used to select inverse
display operation, the column address decoder inverts
the relationship between the RAM column data and the
display segment outputs.
Page Address Register
The 4-bit page address register provides the page address
to display data RAM. The contents of the register are
changed by the Page Address Set command.
Page address 8 (D3 = HIGH, D2, D1, D0 = LOW) is a
special use RAM area for the indicator.
Initial Display Line Register
The initial display line register stores the address of the
RAM line that corresponds to the first (normally the top)
Rev. 4.6
D0
D1
D2
D3
D4
1
0
1
0
0
Figure 5. RAM-to-LCD data transfer
EPSON
The time taken to transfer data is very short, because the
microprocessor inputs D0 to D7 correspond to the LCD
common lines as shown in figure 5. Large display
configurations can thus be created using multiple
S1D15600/601/602.
line (COM0) of the display. See figure 4. The contents
of this 6-bit register are changed by the Initial Display
Line command. At the start of each LCD frame, synchro-
nized with SYNC, the initial line is copied to the line
counter. The line counter is then incremented on the CL
clock signal once for every display line. This generates
the line addresses for the transfer of the 166 bits of RAM
data to the LCD drivers.
If a 1/65 or 1/33 display duty cycle is selected by the Duty
+ 1 command, the line address corresponding to the 65th
or 33rd SYNC signal is changed and the indicator spe-
cial-use line address is selected. If the Duty + 1 command
is not used, the indicator special-use line address is not
selected.
Output Selection Circuit
The number of common (COM) and segment (SEG)
driver outputs can be selected to fit different LCD panel
configurations by the output selection circuit.
There are 70 segment-only outputs (O32 to O101) and 96
common or segment dual outputs (O0 to O31 and O102
to O165). A command select the status of the dual
common/segment outputs. Figure 6 shows the six differ-
ent LCD driver arrangements.
Necessary LCD driver voltage is automatically allocated
to the COM/SEG dual outputs when their function is
determined by the output selection circuit.
The S1D15600 selects Case 1, 2 or 6 while the S1D15601
selects Case 3, 4, 5 or 6. As to the S1D15602, COM/SEG
output status cannot be selected, being fixed.
COM0
COM1
COM2
COM3
COM4
S1D15600/601/602 Series
7–25