AD7265BSUZ Analog Devices Inc, AD7265BSUZ Datasheet - Page 13

• Manufacturer Part Number: AD7265BSUZ
• Description: IC,Data Acquisition System,3-CHANNEL,12-BIT,TQFP,32PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7265BSUZ

• Design Resources: AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 21mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Number Of Elements: 2
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 1MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5/5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 21mW
• Differential Linearity Error: -0.99LSB/1.5LSB
• Integral Nonlinearity Error: ±1.5LSB
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7265CB - BOARD EVALUATION FOR AD7265
• Lead Free Status / Rohs Status: Compliant

THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7265 is a fast, micropower, dual, 12-bit, single-supply,
ADC that operates from a 2.7 V to a 5.25 V supply. When
operated from either a 3 V or a 5 V supply, the AD7265 is
capable of throughput rates of 1 MSPS when provided with a
16 MHz clock.
The AD7265 contains two on-chip, differential track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. It is housed in a
32-lead LFCSP or a 32-lead TQFP, offering the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part, but also
provides the clock source for each successive approximation
ADC. The analog input range for the part can be selected to be
a 0 V to V
single-ended or differential analog inputs. The AD7265 has an
on-chip 2.5 V reference that can be overdriven when an external
reference is preferred. If the internal reference is to be used
elsewhere in a system, then the output needs to be buffered first.
The AD7265 also features power-down options to allow power
saving between conversions. The power-down feature is
implemented via the standard serial interface, as described in
the
CONVERTER OPERATION
The AD7265 has two successive approximation ADCs, each
based around two capacitive DACs.
show simplified schematics of one of these ADCs in acquisition
and conversion phase, respectively. The ADC is comprised of
control logic, a SAR, and two capacitive DACs. In Figure 16 (the
acquisition phase), SW3 is closed, SW1 and SW2 are in Position A,
the comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
Modes of Operation section.
V
V
IN+
IN–
REF
B
B
A
A
V
input or a 2 × V
REF
SW1
SW2
Figure 16. ADC Acquisition Phase
C
C
S
S
SW3
REF
COMPARATOR
input, configured with either
Figure 16 and Figure 17
CAPACITIVE
CAPACITIVE
CONTROL
DAC
DAC
LOGIC
Rev. A | Page 13 of 28
When the ADC starts a conversion (see Figure 17), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the V
otherwise, the two inputs will have different settling times,
resulting in errors.
ANALOG INPUT STRUCTURE
Figure 18 shows the equivalent circuit of the analog input
structure of the AD7265 in differential/pseudo differential
modes. In single-ended mode, V
The four diodes provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signals never
exceed the supply rails by more than 300 mV. This causes these
diodes to become forward-biased and starts conducting into the
substrate. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
The C1 capacitors in Figure 18 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 Ω.
The C2 capacitors are the ADC’s sampling capacitors with a
capacitance of 45 pF typically.
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins with optimum
values of 47 Ω and 10 pF. In applications where harmonic
distortion and signal-to-noise ratio are critical, the analog input
should be driven from a low impedance source. Large source
impedances significantly affect the ac performance of the ADC
and may necessitate the use of an input buffer amplifier. The
choice of the op amp is a function of the particular application.
V
V
IN+
IN–
B
A
A
B
V
REF
SW1
SW2
Figure 17. ADC Conversion Phase
C
C
S
S
IN+
and V
SW3
IN−
COMPARATOR
IN−
pins must be matched;
is internally tied to AGND.
CAPACITIVE
CAPACITIVE
CONTROL
DAC
LOGIC
DAC
AD7265