AD7265BSUZ Analog Devices Inc, AD7265BSUZ Datasheet - Page 21

• Manufacturer Part Number: AD7265BSUZ
• Description: IC,Data Acquisition System,3-CHANNEL,12-BIT,TQFP,32PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7265BSUZ

• Design Resources: AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 21mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Number Of Elements: 2
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 1MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5/5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 21mW
• Differential Linearity Error: -0.99LSB/1.5LSB
• Integral Nonlinearity Error: ±1.5LSB
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7265CB - BOARD EVALUATION FOR AD7265
• Lead Free Status / Rohs Status: Compliant

POWER-UP TIMES
As described in detail, the AD7265 has two power-down
modes, partial power-down and full power-down. This section
deals with the power-up time required when coming out of
either of these modes. It should be noted that the power-up
times, as explained in this section, apply with the recommended
capacitors in place on the D
To power up from full power-down (whether using an internal
or external reference), approximately 1.5 ms should be allowed
from the falling edge of CS , shown as t
Powering up from partial power-down requires much less time.
The power-up time from partial power-down is typically 1 μs;
however, if using the internal reference, then the AD7265 must
be in partial power-down for at least 67 μs in order for this
power-up time to apply.
When power supplies are first applied to the AD7265, the ADC
may power up in either of the power-down modes or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure the part is fully powered up before attempting a
valid conversion. Likewise, if it is intended to keep the part in
the partial power-down mode immediately after the supplies are
applied, then two dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10
edge (see Figure 34); in the second cycle, CS must be brought
high before the 10
falling edge (see Figure 35). Alternatively, if it is intended to
place the part in full power-down mode when the supplies are
applied, then three dummy cycles must be initiated. The first
dummy cycle must hold CS low until after the 10
edge (see Figure 34); the second and third dummy cycles place
the part in full power-down (see Figure 37).
Once supplies are applied to the AD7265, enough time must be
allowed for any external reference to power up and charge the
various reference buffer decoupling capacitors to their final values.
POWER vs. THROUGHPUT RATE
The power consumption of the AD7265 varies with throughput
rate. When using very slow throughput rates and as fast an
SCLK frequency as possible, the various power-down options
D
D
SCLK
OUT
OUT
CS
A
B
th
SCLK edge but after the second SCLK
1
CAP
A and D
THE PART BEGINS
TO POWER UP.
POWER-UP2
CAP
INVALID DATA
B pins.
in Figure 38.
t
POWER-UP2
th
th
SCLK falling
SCLK falling
Figure 38. Exiting Full Power-Down Mode
10
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can be used to make significant power savings. However, the
AD7265 quiescent current is low enough that even without
using the power-down options, there is a noticeable variation in
power consumption with sampling rate. This is true whether a
fixed SCLK value is used or if it is scaled with the sampling rate.
Figure 39 and Figure 40 show plots of power vs. the throughput
rate when operating in normal mode for a fixed maximum
SCLK frequency, and an SCLK frequency that scales with the
sampling rate with V
cases, the internal reference was used.
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
25
23
21
19
17
15
13
11
Figure 39. Power vs. Throughput in Normal Mode with V
Figure 40. Power vs. Throughput in Normal Mode with V
9
7
5
0
0
T
T
A
A
= 25°C
= 25°C
100
100
1
THE PART IS FULLY POWERED UP,
SEE POWER-UP TIMES SECTION.
VARIABLE SCLK
200
200
VALID DATA
DD
300
300
THROUGHPUT (kSPS)
= 3 V and V
THROUGHPUT (kSPS)
400
400
500
500
VARIABLE SCLK
14
16MHz SCLK
600
600
DD
16MHz SCLK
= 5 V, respectively. In all
700
700
800
800
900
900
AD7265
DD
DD
1000
1000
= 3 V
= 5 V