AD7265BSUZ Analog Devices Inc, AD7265BSUZ Datasheet - Page 20

• Manufacturer Part Number: AD7265BSUZ
• Description: IC,Data Acquisition System,3-CHANNEL,12-BIT,TQFP,32PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7265BSUZ

• Design Resources: AD7265 in Differential and Single-Ended Configurations Using AD8022 (CN0048)
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 21mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Number Of Elements: 2
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 1MSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: 2.5/5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 21mW
• Differential Linearity Error: -0.99LSB/1.5LSB
• Integral Nonlinearity Error: ±1.5LSB
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 32
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7265CB - BOARD EVALUATION FOR AD7265
• Lead Free Status / Rohs Status: Compliant

AD7265
To exit this mode of operation and power up the AD7265 again,
a dummy conversion is performed. On the falling edge of CS ,
the device begins to power up and continues to power up as
long as CS is held low until after the falling edge of the 10
SCLK. The device is fully powered up after approximately 1 μs
has elapsed, and valid data results from the next conversion, as
shown in Figure 36. If CS is brought high before the second
falling edge of SCLK, the AD7265 again goes into partial
power-down. This avoids accidental power-up due to glitches
on the CS line. Although the device may begin to power up on
the falling edge of CS , it powers down again on the rising edge
of CS . If the AD7265 is already in partial power-down mode
and CS is brought high between the second and 10
edges of SCLK, the device enters full power-down mode.
FULL POWER-DOWN MODE
This mode is intended for use in applications where throughput
rates slower than those in the partial power-down mode are
required, as power-up from a full power-down takes
substantially longer than that from partial power-down. This
mode is more suited to applications where a series of
conversions performed at a relatively high throughput rate are
followed by a long period of inactivity and thus power-down.
D
D
D
D
SCLK
SCLK
OUT
OUT
OUT
OUT
CS
CS
A
B
A
B
THE PART BEGINS
TO POWER UP.
1
1
2
INVALID DATA
PARTIAL POWER DOWN.
THE PART ENTERS
INVALID DATA
t
POWER-UP1
th
Figure 36. Exiting Partial Power-Down Mode
10
Figure 37. Entering Full Power-Down Mode
falling
10
THREE-STATE
th
Rev. A | Page 20 of 28
14
14
THE PART BEGINS
TO POWER UP.
When the AD7265 is in full power-down, all analog circuitry is
powered down. Full power-down is entered in a similar way as
partial power-down, except the timing sequence shown in
Figure 35 must be executed twice. The conversion process must
be interrupted in a similar fashion by bringing CS high anywhere
after the second falling edge of SCLK and before the 10
edge of SCLK. The device enters partial power-down at this
point. To reach full power-down, the next conversion cycle
must be interrupted in the same way, as shown in Figure 37.
Once CS is brought high in this window of SCLKs, the part
completely powers down.
Note that it is not necessary to complete the 14 SCLKs once
is brought high to enter a power-down mode.
To exit full power-down and power up the AD7265, a dummy
conversion is performed, as when powering up from partial
power-down. On the falling edge of CS , the device begins to
power up and continues to power up, as long as CS is held low
until after the falling edge of the 10
power-up time must elapse before a conversion can be initiated,
as shown in Figure 38. See the Power-Up Times section for the
power-up times associated with the AD7265.
1
2
INVALID DATA
1
THE PART IS FULLY
POWERED UP; SEE
POWER-UP TIMES
SECTION.
FULL POWER DOWN.
THE PART ENTERS
VALID DATA
10
THREE-STATE
14
th
SCLK. The required
14
th
falling
CS