CS5376A-IQZ Cirrus Logic Inc, CS5376A-IQZ Datasheet - Page 20

• Manufacturer Part Number: CS5376A-IQZ
• Description: IC,Digital Filter,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5376A-IQZ

• Filter Type: Digital
• Number Of Filters: 4
• Max-order: 2nd
• Voltage - Supply: 3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Operating Temperature: -40 to 85 °C
• Resolution (bits): 24bit
• Conversion Rate: 4kSPS
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 64
• Msl: MSL 3 - 168 Hours
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376
• Frequency - Cutoff Or Center: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3 Clock Generation
A single 32.768 MHz low-jitter clock input, which
can be generated from a VCXO based PLL, is re-
quired to drive the CS5376A device. Clock inputs
for other system devices are driven by clock out-
puts from the CS5376A.
3.4 Synchronization
Digital filter phase and analog sample timing of the
four ∆Σ modulators connected to the CS5376A are
synchronized by a rising edge on the SYNC pin. If
a synchronization signal is received identically by
all CS5376A devices in a measurement network,
synchronous sampling across the network is guar-
anteed.
3.5 System Configuration
Through the SPI 1 serial port, filter coefficients and
digital filter register settings can either be pro-
grammed by a microcontroller or automatically
loaded from an external EEPROM after reset. Sys-
tem configuration is only required for the
CS5376A device, as other devices are configured
via the CS5376A General Purpose I/O pins.
Two registers in the digital filter, SYSTEM1 and
SYSTEM2 (0x2C, 0x2D), are provided for user de-
fined system information. These are general pur-
pose registers that will hold any 24-bit data values
written to them.
3.6 Digital Filter Operation
After analog to digital conversion occurs in the
modulators, the oversampled 1-bit ∆Σ data is read
into the CS5376A through the MDATA pins. The
digital filter then processes data through the en-
abled filter stages, decimating it to 24-bit words at
a programmed output word rate. The final 24-bit
samples are concatenated with 8-bit status words
and placed into an output FIFO.
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3.7 Data Collection
Data is collected from the CS5376A through the
Serial Data port (SD port). Automatically or upon
request, depending how the SDTKI pin is connect-
ed, the SD port initiates serial transactions to trans-
fer 32-bit data from the output FIFO to the system
telemetry. The output FIFO has eight data locations
to permit latency in data collection.
3.8 Integrated peripherals
Test Bit Stream (TBS)
A digital signal generator built into the CS5376A
produces a 1-bit ∆Σ sine wave. This digital test bit
stream can be connected to the CS4373A test DAC
to create high quality analog test signals or it can be
internally looped back to the CS5376A MDATA
inputs to test the digital filter and data collection
circuitry.
Time Break
Timing information is recorded during data collec-
tion by strobing the TIMEB pin. A dedicated flag
in the sample status bits, TB, is set high to indicate
over which measurement the timing event oc-
curred.
General Purpose I/O (GPIO)
Twelve general purpose pins are available on the
CS5376A for system control. Each pin can be set as
input or output, high or low, with an internal pull-
up enabled or disabled. The CS3301A/02A,
CS5371A/72A and CS4373A devices in Figure 9
are configured by simple pin settings controlled
through the CS5376A GPIO pins.
Serial Peripheral Interface 2 (SPI 2)
A secondary master mode serial port to communi-
cate with external serial peripherals.
JTAG Port
Boundary scan JTAG is IEEE 1149.1 compliant.
CS5376A
DS612F4