CS5376A-IQZ Cirrus Logic Inc, CS5376A-IQZ Datasheet - Page 25

• Manufacturer Part Number: CS5376A-IQZ
• Description: IC,Digital Filter,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5376A-IQZ

• Filter Type: Digital
• Number Of Filters: 4
• Max-order: 2nd
• Voltage - Supply: 3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Operating Temperature: -40 to 85 °C
• Resolution (bits): 24bit
• Conversion Rate: 4kSPS
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 64
• Msl: MSL 3 - 168 Hours
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376
• Frequency - Cutoff Or Center: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7. SYNCHRONIZATION
The CS5376A has a dedicated SYNC input that
aligns the internal digital filter phase and generates
an external signal for synchronizing modulator an-
alog sampling. By providing simultaneous rising
edges to the SYNC pins of multiple CS5376A de-
vices, synchronous sampling across a network can
be guaranteed.
7.1 Pin Description
SYNC - Pin 59
Synchronization input, rising edge triggered.
7.2 MSYNC Generation
The SYNC signal rising edge is used to generate a
retimed synchronization signal, MSYNC. The
MSYNC signal reinitializes internal digital filter
phase and is driven onto the MSYNC output pin to
phase align modulator analog sampling.
The MSEN bit in the digital filter CONFIG register
(0x00) enables MSYNC generation. See “Modula-
tor Interface” on page 39 for more information
about MSYNC.
7.3 Digital Filter Synchronization
The internal MSYNC signal resets the digital filter
state machine to establish a known digital filter
DS612F4
SYNC
MSEN
0
1
Figure 13. Synchronization Block Diagram
Generator
MSYNC
phase. Filter convolutions restart, and the next out-
put word is available one full sample period later.
Repetitive synchronization is supported when
SYNC events occur at exactly the selected output
word rate. In this case, re-synchronization occurs at
the start of a convolution cycle when the digital fil-
ter state machine is already reset.
7.4 Modulator Synchronization
The external MSYNC signal phase aligns modula-
tor analog sampling when connected to the
CS5371A/72A MSYNC input. This ensures syn-
chronous analog sampling relative to MCLK.
Repetitive synchronization of the modulators is
supported when SYNC events occur at exactly the
selected output word rate. In this case, synchroni-
zation will occur at the start of analog sampling.
7.5 Test Bit Stream Synchronization
When the test bit stream generator is enabled, an
MSYNC signal can reset the internal data pointer.
This restarts the test bit stream from the first data
point to establish a known output signal phase.
The TSYNC bit in the digital filter TBSCFG regis-
ter (0x2A) enables synchronization of the test bit
stream by MSYNC. When TSYNC is disabled, the
test bit stream phase is not affected by MSYNC.
Digital
Filter
MSYNC
Output
TSYNC
0
1
Test Bit
CS5376A
Stream
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