CS5376A-IQZ Cirrus Logic Inc, CS5376A-IQZ Datasheet - Page 7

• Manufacturer Part Number: CS5376A-IQZ
• Description: IC,Digital Filter,QFP,64PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5376A-IQZ

• Filter Type: Digital
• Number Of Filters: 4
• Max-order: 2nd
• Voltage - Supply: 3 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Package: 64TQFP
• Operating Temperature: -40 to 85 °C
• Resolution (bits): 24bit
• Conversion Rate: 4kSPS
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 64
• Msl: MSL 3 - 168 Hours
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1778 - EVALUATION BOARD FOR CS5376
• Frequency - Cutoff Or Center: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. GENERAL DESCRIPTION
The CS5376A is a multi-channel digital filter with
integrated system peripherals. Figure 1 illustrates a
simplified block diagram of the CS5376A.
1.1 Digital Filter Features
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DS612F4
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Multi-channel
CS5371A/72A ∆Σ modulators.
Synchronous operation for simultaneous sam-
pling in multi-sensor systems.
Multiple output word rates, including low
bandwidth rates.
1, 2, 3, or 4 channel concurrent operation.
Internal synchronization of digital filter
phase to an external SYNC signal.
Standard output rates: 4000, 2000, 1000,
500, 333, 250 SPS.
decimation
Interface
JTAG
Serial Data Output Port
Filtering Engine
Decimation and
Figure 1. CS5376A Block Diagram
filter
Modulator Data
Interface
for
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Flexible digital filter configuration. (See Figure
2)
Digital gain correction.
Serial Peripheral Interface 1
Serial Peripheral Interface 2
Test Bit Stream Controller
Time Break Controller
General Purpose I/O
Low bandwidth rates: 200, 125, 100, 50, 40,
25, 20, 10, 5, 1 SPS.
Cascaded SINC, FIR, and IIR filters with
selectable output stage.
Linear and minimum phase FIR low-pass
filter coefficients included.
3 Hz Butterworth IIR high-pass filter coef-
ficients included.
FIR and IIR coefficients are programmable
to create a custom filter response.
Individual channel gain correction to nor-
malize signal amplitudes.
Synchronization
Clock and
SPI 1
GPIO
SPI 2
CLK
SYNC
MCLK
MSYNC
SSI
SCK1
MISO
MOSI
SINT
TIMEB
TBSCLK
TBSDATA
GPIO11:EECS
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4:CS4
GPIO3:CS3
GPIO2:CS2
GPIO1:CS1
GPIO0:CS0
SCK2
SO
SI1
SI2
SI3
SI4
CS5376A
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