CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 33

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

DS692PP1
6.6.2
6.7
Non-Audio Detection
An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in-
coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit
1, which is extracted automatically by the CS8422. However, certain non-audio sources, such as AC-3
MPEG encoders, may not adhere to this convention and the bit may not be properly set. The CS8422 AES3
receiver can detect such non-audio data through the use of an auto-detect module. The auto-detect module
is similar to auto-detect software used in Cirrus Logic DSPs.
If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS
internal AUTODETECT signal will be asserted. If the sync codes no longer appear after a certain amount
of time, auto-detection will time-out and AUTODETECT will be de-asserted until another format is detected.
The AUDIO signal is the logical OR of AUTODETECT and the received channel status bit 1.
In Software Mode AUDIO is available through the GPO pins. If non-audio data is detected, the data is still
processed exactly as if it were normal audio. The exception is the use of de-emphasis auto-select feature
which will bypass the de-emphasis filter if the input stream is detected to be non-audio. It is up to the user
to mute the outputs as required.
The error bits are “sticky”, meaning that they are set on the first occurrence of the associated error and
will remain set until the user reads the register through the control port. This enables the register to log all
unmasked errors that occurred since the last time the register was read.
As a result of the bits “stickiness”, it is necessary to perform two reads on these registers to see if the error
condition still exists.
The Receiver Error Mask register (0Eh) allows masking of individual errors. The bits in this register default
to 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to
1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error
register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio
sample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, which
do not affect the current audio sample, even if unmasked.
The HOLD bits allow a choice of:
For more details, refer to
page
(14h)” on page
Hardware Mode Control
In Hardware Mode, the user may choose to output either the Non-Validity Receiver Error (NVERR) or the
Receiver Error (RERR) on the NV/RERR pin. By default the pin will output the NRERR signal. If upon star-
tup a 20 kΩ resistor is connected between the pin and VL, the NV/RERR pin will output the RERR error
signal. Both RERR and NVERR are updated on AES3 subframe boundaries. See
trol” on page 39
NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi-
phase, confidence or PLL lock error occurs during the current sample.
RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit is
high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample.
– Holding the previous sample
– Replacing the current sample with zero (mute)
– Not changing the current audio sample
56,
“Interrupt Mode (10h)” on page
59.
for more details.
“Receiver Error Unmasking (0Eh)” on page
57,
“Receiver Error (13h)” on page
56,
“Interrupt Unmasking (0Fh)” on
58, and
®
“Hardware Mode Con-
data transmission, an
“Interrupt Status
CS8422
®
33
or