CS8422-DNZR Cirrus Logic Inc, CS8422-DNZR Datasheet - Page 52

• Manufacturer Part Number: CS8422-DNZR
• Description: IC 24-bit 192kHz SRC S/PDIF Receiver
• Manufacturer: Cirrus Logic Inc

52
11.9
11.10 Data Routing Control(0Ah)
SDOUT1(1)
RMCK3
7
0
7
0
SRC_MCLK[1:0] - Controls the master clock (MCLK) source for the sample rate converter. See
ter Clock” on page 38
SRC_DIV – Divide-by-two for the SRC MCLK source. Valid only if SRC_MCLK = 00.
Recovered Master Clock Ratio Control & Misc. (09h)
RMCK[3:0] – Selects the RMCK/Fsi ratio, where Fsi is the sample rate of the incoming AES3-compatible
data or ISCLK/64. Note: If a serial audio output port is in master mode and sourced directly by the AES3
receiver, then RMCK is the master clock source for the selected serial output port and RMCK[3:0] determine
the MCLK/OLRCK ratio for the selected serial output port.
SRC_MUTE – When SRC_MUTE is set to ‘1’, the SRC will soft-mute when it loses lock and soft unmute
when it regains lock.
SDOUT1[1:0] - Controls the data source for SDOUT1
1 - RMCK
00 - XTI-XTO. If XTI is connected to GND or VL and XTO is left floating, the SRC MCLK will be the internal
ring oscillator.
01 - PLL clock
10 - Internal Ring Oscillator
11 - Reserved
0 - SRC MCLK is not divided. Maximum allowable SRC MCLK frequency is 33 MHz.
1 - SRC MCLK is divided. Maximum allowable SRC MCLK frequency is 49.152 MHz.
0000 - RMCK = 64 x Fsi
0001 - RMCK = 96 x Fsi
0010 - RMCK = 128 x Fsi
0011 - RMCK = 192 x Fsi
0100 - RMCK = 256 x Fsi
0101 - RMCK = 384 x Fsi
0110 - RMCK = 512 x Fsi
0111 - RMCK = 768 x Fsi
1000 - RMCK = 1024 x Fsi
0 - Soft mute disabled
1 - Soft mute enabled
SDOUT1(0)
RMCK2
6
0
6
0
SDOUT2(1)
for details.
RMCK1
5
0
5
0
SDOUT2(0)
RMCK0
4
0
4
1
SRC_MUTE
MUTESAO1
3
1
3
0
MUTESAO2
Reserved
2
2
0
Reserved
SRCD
1
1
0
CS8422
Reserved
Reserved
DS692PP1
“SRC Mas-
0
0