DSPIC30F2010-20E/SO Microchip Technology, DSPIC30F2010-20E/SO Datasheet - Page 117

• Manufacturer Part Number: DSPIC30F2010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.7.3.3
The following configuration items are required to
achieve a 600 ksps conversion rate.
• Comply with conditions provided in
• Connect external V
• Set SSRC<2:0> = 111 in the ADCON1 register to
• Enable automatic sampling by setting the ASAM
• Enable sequential sampling by clearing the
• Enable at least two sample and hold channels by
• Write the SMPI<3:0> control bits in the ADCON2
• Configure the A/D clock period to be:
• Configure the sampling time to be 2 T
Select at least two channels per analog input pin by
writing to the ADCHS register.
FIGURE 18-3:
© 2011 Microchip Technology Inc.
the recommended circuit shown in
enable the auto-convert option
control bit in the ADCON1 register
SIMSAM bit in the ADCON1 register
writing the CHPS<1:0> control bits in the
ADCON2 register
register for the desired number of conversions
between interrupts. At a minimum, set
SMPI<3:0> = 0001 since at least two sample and
hold channels should be enabled
by writing to the ADCS<5:0> control bits in the
ADCON3 register
writing: SAMC<4:0> = 00010
Note: C
Legend: C
PIN
VA
12 x 600,000
value depends on device package and is not tested. Effect of C
600 ksps Configuration Items
Rs
1
V
I leakage
R
R
C
ANx
PIN
T
IC
SS
HOLD
REF
C
ADC ANALOG INPUT MODEL
PIN
+ and V
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
REF
= 138.89 ns
- pins following
Figure 18-2
Table 18-2
V
AD
DD
by
V
V
T
T
= 0.6V
= 0.6V
R
I leakage
± 500 nA
IC
≤ 250Ω
18.8
The analog input model of the 10-bit ADC is shown in
Figure
function of the internal amplifier settling time, device
V
For the A/D converter to meet its specified accuracy, the
charge holding capacitor (C
fully charge to the voltage level on the analog input pin.
The
impedance (R
(R
required to charge the capacitor C
impedance of the analog sources must therefore be
small enough to fully charge the holding capacitor within
the chosen sample time. To minimize the effects of pin
leakage currents on the accuracy of the A/D converter,
the maximum recommended source impedance, R
5 kΩ. After the analog input channel is selected
(changed), this sampling function must be completed
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
The user must allow at least 1 T
time, T
ple to be acquired. This sample time may be controlled
manually in software by setting/clearing the SAMP bit,
or it may be automatically controlled by the A/D con-
verter. In an automatic configuration, the user must
allow enough time between conversion triggers so that
the minimum sample time can be satisfied. Refer to the
Electrical Specifications for T
requirements.
DD
SS
and the holding capacitor charge time.
) impedance combine to directly affect the time
PIN
source
SAMP
18-3. The total sampling time for the A/D is a
A/D Acquisition Requirements
negligible if Rs ≤ 5 kΩ.
Sampling
Switch
, between conversions to allow each sam-
IC
R
impedance
SS
), and the internal sampling switch
dsPIC30F2010
R
SS
V
SS
C
= DAC capacitance
= 4.4 pF
≤ 3 kΩ
HOLD
HOLD
(R
S
AD
AD
),
) must be allowed to
HOLD
period of sampling
and sample time
DS70118J-page 117
the
. The combined
interconnect
S
, is