DSPIC30F2010-20E/SO Microchip Technology, DSPIC30F2010-20E/SO Datasheet - Page 197

• Manufacturer Part Number: DSPIC30F2010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TimerQ (QEI Module) External Clock
Timing Characteristics
Timing Diagrams
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
© 2011 Microchip Technology Inc.
Timing Characteristics .............................................. 165
A/D Conversion
Band Gap Start-up Time ........................................... 162
CLKO and I/O ........................................................... 160
External Clock........................................................... 156
I
I
Input Capture (CAPx)................................................ 166
Motor Control PWM Module...................................... 168
Motor Control PWM Module Fault............................. 168
OC/PWM Module ...................................................... 167
Oscillator Start-up Timer ........................................... 161
Output Compare Module........................................... 166
Power-up Timer ........................................................ 161
QEI Module Index Pulse ........................................... 170
Reset......................................................................... 161
SPI Module
TimerQ (QEI Module) External Clock ....................... 165
Type A and B Timer External Clock.......................... 163
Watchdog Timer........................................................ 161
Center-Aligned PWM .................................................. 85
Dead-Time .................................................................. 87
Edge-Aligned PWM..................................................... 85
PWM Output ............................................................... 73
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
DC Characteristics - Internal RC Accuracy............... 159
A/D Conversion
Band Gap Start-up Time ........................................... 162
Brown-out Reset ....................................................... 161
CLKO and I/O ........................................................... 160
External Clock........................................................... 157
I
I
Input Capture ............................................................ 166
Motor Control PWM Module...................................... 168
Oscillator Start-up Timer ........................................... 161
Output Compare Module........................................... 166
Power-up Timer ........................................................ 161
QEI Module
2
2
2
2
C Bus Data
C Bus Start/Stop Bits
C Bus Data (Master Mode)..................................... 177
C Bus Data (Slave Mode)....................................... 179
10-Bit High-speed (CHPS = 01, SIMSAM = 0,
10-bit High-speed (CHPS = 01, SIMSAM = 0,
Master Mode ..................................................... 176
Slave Mode ....................................................... 178
Master Mode ..................................................... 176
Slave Mode ....................................................... 178
Master Mode (CKE = 0) .................................... 171
Master Mode (CKE = 1) .................................... 172
Slave Mode (CKE = 0) ...................................... 173
Slave Mode (CKE = 1) ...................................... 174
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
High-speed ....................................................... 184
External Clock................................................... 165
Index Pulse ....................................................... 170
ASAM = 0, SSRC = 000) .......................... 182
ASAM = 1, SSRC = 111, SAMC = 00001) 183
DD
).......................................... 128
DD
DD
), Case 1...................... 128
), Case 2...................... 128
Timing Specifications
U
UART
Unit ID Locations .............................................................. 121
Universal Asynchronous Receiver Transmitter. See UART.
W
Wake-up from Sleep ......................................................... 121
Wake-up from Sleep and Idle ............................................. 41
Watchdog Timer
Watchdog Timer (WDT)............................................ 121, 131
WWW Address ................................................................. 199
WWW, On-Line Support ....................................................... 6
Quadrature Decoder................................................. 169
Reset ........................................................................ 161
Simple OC/PWM Mode ............................................ 167
SPI Module
Type A Timer External Clock.................................... 163
Type B Timer External Clock.................................... 164
Type C Timer External Clock.................................... 164
Watchdog Timer ....................................................... 161
PLL Clock ................................................................. 158
Address Detect Mode ............................................... 107
Auto Baud Support ................................................... 107
Baud Rate Generator ............................................... 107
Enabling and Setting Up UART ................................ 105
Loopback Mode ........................................................ 107
Module Overview...................................................... 103
Operation During CPU Sleep and Idle Modes.......... 108
Receiving Data ......................................................... 106
Reception Error Handling ......................................... 106
Transmitting Data ..................................................... 105
UART1 Register Map ............................................... 109
Timing Characteristics .............................................. 161
Timing Requirements ............................................... 161
Enabling and Disabling............................................. 131
Operation.................................................................. 131
Master Mode (CKE = 0).................................... 171
Master Mode (CKE = 1).................................... 172
Slave Mode (CKE = 0)...................................... 173
Slave Mode (CKE = 1)...................................... 175
Alternate I/O ..................................................... 105
Disabling........................................................... 105
Enabling ........................................................... 105
Setting Up Data, Parity and
In 8-bit or 9-bit Data Mode................................ 106
Interrupt ............................................................ 106
Receive Buffer (UxRXB)................................... 106
Framing Error (FERR) ...................................... 107
Idle Status ........................................................ 107
Parity Error (PERR) .......................................... 107
Receive Break .................................................. 107
Receive Buffer Overrun Error (OERR Bit) ........ 106
In 8-bit Data Mode ............................................ 105
In 9-bit Data Mode ............................................ 105
Interrupt ............................................................ 106
Transmit Buffer (UxTXB) .................................. 105
Stop Bit Selections ................................... 105
dsPIC30F2010
DS70118J-page 197