DSPIC30F2010-20E/SO Microchip Technology, DSPIC30F2010-20E/SO Datasheet - Page 133

• Manufacturer Part Number: DSPIC30F2010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 19-7:
TABLE 19-8:
RCON
OSCCON
Legend:
Note
FOSC
FWDT
FBORPOR F80004
FBS
FSS
FGS
FICD
Legend:
Note
SFR Name
Name
1:
1:
2:
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Refer to the “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
Reserved bits read as ‘1’ and must be programmed as ‘1’.
Address
F80000
F80002
F80006
F80008
F8000A
F8000C
— = unimplemented bit
— = unimplemented bit
Addr.
0740
0742
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
TRAPR
Bit 15
TUN3
FWDTEN
MCLREN
BKBUG
Bit 15
FCKSM<1:0>
—
—
—
IOPUWR
Bit 14
TUN2
Bit 14
COE
—
—
—
—
—
Bit 13
BGST
COSC<1:0>
Bit 13
—
—
—
—
—
Reserved
Reserved
Bit 12
—
Bit 12
(2)
(2)
Bit 11
TUN1
—
—
—
—
—
—
Bit 10
TUN0
Bit 11
—
—
—
—
—
—
—
—
Bit 9
NOSC<1:0>
—
PWMPIN
(1)
Bit 10
—
—
—
—
—
—
Bit 8
(1)
—
EXTR
Bit 7
POST<1:0>
HPOL
Bit 9
—
—
—
—
Reserved
FOS<1:0>
SWR
Bit 6
Reserved
LPOL
Bit 8
(2)
SWDTEN
—
—
—
LOCK
Bit 5
(2)
BOREN
Bit 7
WDTO
—
—
—
—
—
—
Bit 4
—
SLEEP
Bit 6
Bit 3
—
—
—
—
—
—
—
CF
Bit 2
IDLE
—
Bit 5
—
FWPSA<1:0>
—
—
—
—
BORV<1:0>
LPOSCEN
Bit 1
BOR
Bit 4
—
—
—
—
—
OSWEN Depends on Configuration bits
Bit 0
POR
Bit 3
—
—
—
Depends on type of Reset
Reserved
Bit 2
FWPSB<3:0>
—
—
Reserved
Reserved
FPR<3:0>
(2)
Reset State
(2)
(2)
Bit 1
GCP
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0