DSPIC30F2010-20E/SO Microchip Technology, DSPIC30F2010-20E/SO Datasheet - Page 27

• Manufacturer Part Number: DSPIC30F2010-20E/SO
• Description: IC,DSP,16-BIT,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
3.2.6
The dsPIC DSC device contains a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word, and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops,
and post-increments for stack pushes, as shown in
Figure
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
© 2011 Microchip Technology Inc.
Note:
3-9. Note that for a PC push during any CALL
NEAR DATA SPACE
SOFTWARE STACK
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
There is a Stack Pointer Limit register (SPLIM) associ-
ated with the Stack Pointer. SPLIM is uninitialized at
Reset. As is the case for the Stack Pointer, SPLIM<0>
is forced to ‘0’, because all stack operations must be
word-aligned. Whenever an EA is generated using
W15 as a source or destination pointer, the address
thus generated is compared with the value in SPLIM. If
the contents of the Stack Pointer (W15) and the SPLIM
register are equal and a push operation is performed, a
stack error trap will not occur. The stack error trap will
occur on a subsequent push operation. Thus, for exam-
ple, if it is desirable to cause a stack error trap when the
stack grows beyond address 0x2000 in RAM, initialize
the SPLIM with the value, 0x1FFE.
Similarly, a stack pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-9:
0x0000
000000000
15
<Free Word>
dsPIC30F2010
PC<15:0>
PC<22:16>
CALL STACK FRAME
0
W15 (before CALL)
W15 (after CALL)
POP: [--W15]
PUSH: [W15++]
DS70118J-page 27