SL23EP08SI-1 Silicon Laboratories Inc, SL23EP08SI-1 Datasheet - Page 11

• Manufacturer Part Number: SL23EP08SI-1
• Description: Clock Buffer 10-133MHz 8 Out ZDB 3.3-2.5V Fout=Fin
• Manufacturer: Silicon Laboratories Inc

Specifications of SL23EP08SI-1

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Components & Design Considerations
Typical Application Schematic
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between VDD and VSS pins. Place the capacitor on
the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via
should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and
the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 4. Place the series termination
resistors as close to the clock outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay”
between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL, and
sees an additional 4 pF load with respect to Bank A and B clocks. For applications requiring zero input/output delay, the load
at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the
CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN.
Rev 1.0, May 18, 2006
For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same.
CLKIN
VDD
VDD
VDD
0.1μF
0.1μF
S1
S2
1
4
13
8
9
SL23EP08
5
GND
12
GND
16
11
2
3
CL
CL
CLKA1
CLKA2
CLKB4
CL-4pF
FBK
SL23EP08
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