SL23EP08SI-1 Silicon Laboratories Inc, SL23EP08SI-1 Datasheet - Page 3

• Manufacturer Part Number: SL23EP08SI-1
• Description: Clock Buffer 10-133MHz 8 Out ZDB 3.3-2.5V Fout=Fin
• Manufacturer: Silicon Laboratories Inc

Specifications of SL23EP08SI-1

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description-
The SL23EP08 is a low skew, low jitter Zero Delay Buffer
with very low operating current.
The product includes an on-chip high performance PLL that
locks into the input reference clock and produces nine (9)
output clock drivers tracking the input reference clock for
systems requiring clock distribution.
in addition to CLKOUT that is used for internal PLL
feedback, there are two (2) banks with four (4) outputs in
each bank, bringing the number of total available output
clocks to nine (9).
Input and output Frequency Range-
The input and output frequency range is the same. But, the
frequency range depends on VDD and drive levels as given
in the below Table 1.
If the input clock frequency is less than 2 MHz or floating,
this is detected by an input frequency detection circuitry and
all eight (8) clock outputs are forced to Hi-Z. The PLL is
shutdown to save power. In this shutdown state, the product
draws less than 25 μA supply current.
SpreadThru
If a Spread Spectrum Clock (SSC) were to be used as an
input clock, the SL23EP08 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its
reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL and
drivers without any degradation in spread percent (%),
spread profile and modulation frequency
Rev 1.0, May 18, 2006
S2
VDD(V)
3.3
3.3
2.5
2.5
0
0
1
1
Table 1. Input/Output Frequency Range
™
S1
Drive
Feature-
HIGH
HIGH
0
1
0
1
STD
STD
Clock A1-A4 Clock B1-B4 CLKOUT
Min(MHz) Max(MHz)
Tri-state
Driven
Driven
Driven
10
10
10
10
[1]
Tri-state
Tri-state
Driven
Driven
Table 2. Select Input Decoding
220
167
200
133
[1]
Driven (4)
Select Input Control-
The SL23EP08 provides two (2) input select control pins
called S1 and S2. This feature enables users to selects
various states of output clock banks-A and bank-B, output
source and PLL shutdown features as shown in the Table 2.
The S1 (Pin-9) and S2 (Pin-8) inputs include 250 kΩ weak
pull-down resistors to GND.
PLL Bypass Mode
If the S1 and S2 pins are logic Low(0) and High(1)
respectively, the on-chip PLL is shutdown and bypassed,
and all the nine output clocks bank A, bank B and CLKOUT
clocks are driven by directly from the reference input clock.
In this operation mode SL23EP08 works like a non-ZDB
product.
High and Low-Drive Product Options -
The SL23EP08 is offered with High-Drive “-1H” and
Standard-Drive “-1” options. These drive options enable the
users to control load levels, frequency range and EMI
control. Refer to the AC electrical tables for the details.
Skew and Zero Delay -
All outputs should drive the similar load to achieve output-to-
output skew and input-to-output specifications given in the
AC electrical tables. However, Zero delay between input and
outputs can be adjusted by changing the loading of CLKOUT
relative to the banks A and B clocks since CLKOUT is the
feedback to the PLL.
Power Supply Range (VDD)-
The SL23EP08 is designed to operate in a wide power
supply range from 2.3V (Min) to 3.3V (Max). An internal on-
chip voltage regulator is used to supply PLL constant power
supply of 1.8V, leading to a consistent and stable PLL
electrical performance in terms of skew, jitter and power
dissipation. Contact SLI for 1.8V power supply version ZDB
called SL23EPL08.
Driven
Driven
Driven
Output Source
Reference
PLL
PLL
PLL
PLL Shutdown and
Bypass
SL23EP08
Page 3 of 15
Yes
Yes
No
No