SL23EP08SI-1 Silicon Laboratories Inc, SL23EP08SI-1 Datasheet - Page 9

• Manufacturer Part Number: SL23EP08SI-1
• Description: Clock Buffer 10-133MHz 8 Out ZDB 3.3-2.5V Fout=Fin
• Manufacturer: Silicon Laboratories Inc

Specifications of SL23EP08SI-1

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Electrical Specifications: VDD=2.5V+/-10% and 0°C to +70°C Operation (Commercial Grade)
Rev 1.0, May 18, 2006
Symbol Description
FOUT-1
FOUT-2
FOUT-2
DC-1
DC-2
DC-1
DC-2
tr/f-1
tr/f-2
tr/f-3
tr/f-3
SKW-1
SKW-2
SKW-3
SKW-4
tCFD
t2
t3
tLOCK
Output Frequency
Output Frequency
Output Frequency
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
Duty Cycle, -1, -2, -3,-4,-1H
and -5H versions
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
Duty Cycle. -1, -2, -3,-4,-1H
and -5H versions
Rise and Fall Times. -1, -2, -
3, and -4 versions
Rise and Fall Times. -1, -2, -
3, and -4 versions
Rise and Fall Times. -1,1H
and -5H versions
Rise and Fall Times. -1H and
-5H versions
Output-to-Output on same
bank A or B. All versions
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Output Bank-A to Bank-B
Skew. -1-4 and -5H
versions
Device-to-Device Skew.
All versions
CLKIN to FBK Rising Edge
Delay
Delay Time, CLKIN Rising
Edge to CLKOUT Rising
Edge
(Measured at VDD/2)
Part-to-Part Skew
(Measured at VDD/2)
PLL Lock Time
[2]
[2]
CL=15pF, FOUT<66.6MHz and Measured at
Condition
CL=30pf, All devices
CL=20pF, -1H and -5H versions
CL=15pF, -1,-2,-3 and -4 versions
CL=30pF, FOUT=66.6MHz and Measured
at VDD/2
VDD/2
CL=30pF, FOUT=120MHz and Measured
at VDD/2
CL=15pF, FOUT=120MHz and Measured
at VDD/2
Measured between 0.8V and 2.0V
CL=30pF
Measured between 0.8V and 2.0V
CL=15pF
Measured between 0.8V and 2.0V
CL=30pF
Measured between 0.8V and 2.0V
CL=15pF
All outputs are equally loaded. Measured
at VDD/2
All outputs are equally loaded. Measured
at VDD/2
All outputs are equally loaded. Measured
at VDD/2
All outputs are equally loaded. Measured
at VDD/2 and FBK pin
All outputs are equally loaded. Measured
at VDD/2
PLL Bypass mode
PLL enabled @ 3.3V
PLL enabled @2.5V
Measured at VDD/2. Any output to any
output, 3.3V supply
Measured at VDD/2. Any output to any
output, 2.5V supply
Valid on all clock pins from VDD=2.97V
Min
–100
–200
TBD
TBD
-200
40.0
45.0
1.5
10
10
10
–
–
-
-
-
-
-
-
-
-
-
Typ
TBD
50.0
50.0
TBD
130
180
60
60
–
–
–
–
–
-
-
-
-
-
-
-
-
-
SL23EP08
Max
Page 9 of 15
±150
±300
60.0
55.0
TBD
TBD
160
220
200
150
150
300
500
200
100
200
1.6
1.2
1.2
1.0
4.4
1.0
Unit
MHz
MHz
MHz
ms
ns
ns
ns
ns
ps
ps
ps
ps
ps
ns
ps
ps
ps
ps
%
%
%
%