MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 57

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Figure 41:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
COMMAND
A0–A9, A11
BA0, BA1
CLK
CKE
A10
DQ
High-Z
Precharge all
t CKS
active banks
t CMS
Self Refresh Mode
t
SINGLE BANK
AS
PRECHARGE
ALL BANKS
BANK(S)
T0
Notes:
t CKH
t CMH
t
AH
t CK
1. No maximum time limit for self refresh.
2.
3. Self refresh mode not supported on automotive temperature (AT) devices.
t RP
t
XSR requires minimum of 2 clocks regardless of frequency or timing.
T1
NOP
t CH
Enter self refresh mode
t CKS
t CL
REFRESH
AUTO
CLK stable prior to exiting
T2
self refresh mode
≥
t RAS min
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1
(Restart refresh time base)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
Exit self refresh mode
RAS MAX applies to non-self refresh mode.
Tn + 1
NOP
t XSR
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128Mb: x4, x8, x16 SDRAM
or COMMAND
INHIBIT
To + 1
©1999 Micron Technology, Inc. All rights reserved.
Timing Diagrams
To + 2
REFRESH
AUTO
DON’T CARE