MT48LC16M8A2TG-75:G Micron Technology Inc, MT48LC16M8A2TG-75:G Datasheet - Page 60

• Manufacturer Part Number: MT48LC16M8A2TG-75:G
• Description: DRAM Chip SDRAM 128M-Bit 16Mx8 3.3V 54-Pin TSOP-II Tray
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC16M8A2TG-75:G

• Package: 54TSOP-II
• Density: 128 Mb
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 133 MHz
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C

Figure 44:
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
DQML, DQMH
A0–A9, A11
COMMAND
BA0, BA1
DQM /
CKE
A10
CLK
DQ
t CMS
t CKS
t AS
t AS
t AS
Single READ – Without Auto Precharge
ACTIVE
ROW
ROW
BANK
T0
t CMH
t CKH
t AH
t AH
t AH
Notes:
t RCD
t RAS
t RC
t CK
T1
NOP
1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. x16: A9 and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or
DISABLE AUTO PRECHARGE
x8: A11 = “Don’t Care.”
t CMS
t CL
COLUMN m
BANK
T2
READ
t CMH
t CH
CAS Latency
2
T3
NOP
t LZ
3
t AC
60
T4
D
NOP
OUT
t OH
t HZ
3
m
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SINGLE BANKS
PRECHARGE
RAS would be violated.
ALL BANKS
BANK(S)
T5
t RP
T6
NOP
128Mb: x4, x8, x16 SDRAM
©1999 Micron Technology, Inc. All rights reserved.
ACTIVE
ROW
BANK
T7
ROW
Timing Diagrams
T8
NOP
DON’T CARE
UNDEFINED