XC5VLX110T-2FFG1738C Xilinx Inc, XC5VLX110T-2FFG1738C Datasheet - Page 341

• Manufacturer Part Number: XC5VLX110T-2FFG1738C
• Description: FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX110T-2FFG1738C

• Package: 1738FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 110592
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 680
• Ram Bits: 5455872
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Total Ram Bits: 5455872
• Number Of I /o: 680
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1738-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 7-18
Figure 7-18: Instantiate IDELAYCTRL Without LOC Constraints - RDY Unconnected
2.
X-Ref Target - Figure 7-19
Figure 7-19: Instantiate IDELAYCTRL Without LOC Constraints - RDY Connected
REFCLK
When RDY port is connected, an AND gate of width equal to the number of clock
regions is instantiated and the RDY output ports from the instantiated and replicated
IDELAYCTRL instances are connected to the inputs of the AND gate. The tools assign
the signal name connected to the RDY port of the instantiated IDELAYCTRL instance
to the output of the AND gate.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints with the RDY port connected are provided in the Libraries
Guide.
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in
REFCLK
RST
Figure
RST
7-19.
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www.xilinx.com
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all IDELAYCTRL
all IDELAYCTRL
Replicated for
Instantiated by user
REFCLK
RST
REFCLK
RST
REFCLK
RST
Replicated for
Instantiated by user
REFCLK
RST
REFCLK
RST
REFCLK
RST
IDELAYCTRL
IDELAYCTRL
IDELAYCTRL
sites
IDELAYCTRL
IDELAYCTRL
IDELAYCTRL
sites
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RDY
RDY
RDY
Input/Output Delay Element (IODELAY)
RDY
RDY
RDY
Auto-generated by
mapper tool
RDY signal ignored
Auto-generated by
mapper tool
ug190_7_13_041206
ug190_7_14_041306
RDY
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