XC5VLX110T-2FFG1738C Xilinx Inc, XC5VLX110T-2FFG1738C Datasheet - Page 45

• Manufacturer Part Number: XC5VLX110T-2FFG1738C
• Description: FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX110T-2FFG1738C

• Package: 1738FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 110592
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 680
• Ram Bits: 5455872
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Total Ram Bits: 5455872
• Number Of I /o: 680
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1738-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

X-Ref Target - Figure 1-22
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Capable I/O
BUFR Use Models
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
BUFRs are ideal for source-synchronous applications requiring clock domain crossing or
serial-to-parallel conversion. Unlike BUFIOs, BUFRs are capable of clocking logic
resources in the FPGAs other than the IOBs.
Figure 1-22: BUFR Driving Various Logic Resources
BUFIO
BUFR
www.xilinx.com
To Region
Above
To Region
Below
Figure 1-22
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
CLBs
is a BUFR design example.
Block
Block
RAM
RAM
Regional Clocking Resources
DSP
DSP
Tile
Tile
UG190_c1_22_022609
To Center
of Die
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