XC5VLX110T-2FFG1738C Xilinx Inc, XC5VLX110T-2FFG1738C Datasheet - Page 354

• Manufacturer Part Number: XC5VLX110T-2FFG1738C
• Description: FPGA Virtex®-5 Family 110592 Cells 65nm (CMOS) Technology 1V 1738-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX110T-2FFG1738C

• Package: 1738FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 110592
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 680
• Ram Bits: 5455872
• Number Of Logic Elements/cells: 110592
• Number Of Labs/clbs: 8640
• Total Ram Bits: 5455872
• Number Of I /o: 680
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1738-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML523-FXT-UNI-G-J - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-FXT-UNI-G - BOARD EVAL FOR VIRTEX-5HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8: Advanced SelectIO Logic Resources
354
ISERDES Primitive (ISERDES_NODELAY)
•
Figure 8-1
components and features of the block.
X-Ref Target - Figure 8-1
The ISERDES primitive in Virtex-5 devices (shown in
X-Ref Target - Figure 8-2
Dedicated support for Networking interfaces.
CLKDIV
OCLK
Bitslip
CE1
CE2
CLK
RST
D
shows the block diagram of the ISERDES, highlighting all the major
BITSLIP
CE1
CE2
CLK
CLKDIV
D
OCLK
SHIFTIN1
SHIFTIN2
RST
CLKB
Figure 8-2: ISERDES_NODELAY Primitive
Figure 8-1: ISERDES Block Diagram
www.xilinx.com
Module
CE
ISERDES_NODELAY
Primitive
Serial to Parallel
Converter
Figure
BITSLIP
Module
8-2) is ISERDES_NODELAY.
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_8_02_112607
Q1
Q2
Q3
Q4
Q5
Q6
SHIFTOUT1
SHIFTOUT2
ug190_8_01_050906
SHIFTIN1/2
SHIFTOUT1/2
Q1 - Q6